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LC5768VG-12F256I

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Lattice Semiconductor ispMACH 5000VG Family Data Sheet
10
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level.
The ispMACH 5000VG devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides
outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3
(CLK 2 when using the secondary clock). The PLL outputs (CLK_OUT) are routed via a dedicated net to a dedi-
cated pad. Further the buffers at these dedicated pads are regular I/O buffers that can select either the I/O macro-
cell or the CLK_OUT (CLK_OUT0/CLK_OUT1) signal. The CLK_OUT nets are not routed through the GRP.
Additionally, there are two sets of signals used for external control. Each PLL has a set of PLL_RST, PLL_FBK and
PLL_LOCK signals. Figure 10 shows the ispMACH 5000VG PLL block diagram.
Figure 10. PLL Block Diagram
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit.
The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and
clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines in 0.5ns
increments from 0 to 3.5ns. For more information on the PLL, please refer to Technical Note TN1003:
ispMACH
5000VG PLL Usage Guidelines
.
Power Management
The ispMACH 5000VG devices provide unique power management controls. The devices have two power settings,
high power and low power, on a per node basis. Low power consumption is approximately 50% of high power con-
sumption with a timing delay adder (tLP) to the routing delay of the low power node. Each node can be configured
as either high power or low power. However, care should be taken when sharing product terms between nodes with
different power settings.
The ispMACH 5000VG devices also have a power-off feature for unused product terms. By default, any product
term that is not used is configured as such. This allows the device to operate at minimal power consumption with-
out affecting the timing of the design. For more information on power management, please refer to Technical Note
TN1002:
Power Estimation in ispMACH 5000VG Devices
.
SEC_OUT
CLK_OUT
PLL_LOCK
CLK_IN
PLL_RST
PLL_FBK
Input Clock
(M) Divider
Post-scalar
(V) Divider
VCO
and
Phase
Detector
Programable
Delay
Secondary
Clock
(K) Divider
Feedback
Loop
(N) Divider
Clock Net
Clock Net
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
11
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 5000VG devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port has its own sup-
ply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 5000VG family of devices
allows this by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick con-
figuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice's ispVM™ System programming software can either perform the quick configuration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispMACH 5000VG devices provide
In-System Programming (ISP
TM
) capability through their Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE
1532 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-
defined interface.
The ispMACH 5000VG devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 5000VG devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispMACH 5000VG devices during the testing
of a circuit board.
Security Bit
A programmable security bit is provided on the ispMACH 5000VG devices as a deterrent to unauthorized copying
of the array configuration patterns. Once programmed, this bit prevents readback of the programmed pattern by a
device programmer, securing proprietary design from competitors. The security bit also prevents programming and
verification. The entire device must be erased in order to erase the security bit.
Hot Socketing
The ispMACH 5000VG devices are well suited for those applications that require hot socketing capability. Hot sock-
eting a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active
signals.
Density Migration
The ispMACH 5000 family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
12
Absolute Maximum Ratings
1, 2, 3
Supply Voltage (V
CC
). . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.4V
PLL Supply Voltage (V
CCP
) . . . . . . . . . . . . . . . . . . . . -0.5 to 5.4V
Output Supply Voltage (V
CCO
). . . . . . . . . . . . . . . . . . -0.5 to 5.4V
Input Voltage Applied
4
. . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.6V
Tr i-state Output Voltage Applied. . . . . . . . . . . . . . . . . -0.5 to 5.6V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150
°
C
Junction Temperature (Tj) with Power Applied . . . . . -55 to 130
°
C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with Lattice
Thermal Management
document is required.
3. All voltages referenced to GND.
4. Overshoot and Undershoot of -2V to (V
IH
(MAX)+2) volts is permitted for a duration of < 20ns.
Recommended Operating Conditions
Erase Reprogram Specifications
Hot Socketing Characteristics
1,2,3
Symbol Parameter Min Max Units
V
CC
Supply Voltage 3.0 3.6 V
V
CCP
Supply Voltage for PLL block 3.0 3.6 V
V
CCJ
Supply Voltage for IEEE1149.1 Test Access Port 1.65 3.6 V
Tj (Commercial) Junction Commercial Operation 0 90 C
Tj (Industrial) Junction Industrial Operation -40 105 C
Note: V
CCJ
must be set in appropriate range to be compatible with desired LVCMOS standard.
Parameter Min Max Units
Erase/Reprogram Cycle 1000 — Cycles
Symbol Parameter Condition Min Typ Max Units
I
DK
Input or I/O Leakage Current
0
≤
V
IN
≤
V
IH
(MAX) — — +/-100
µ
A
V
IH
(MAX)
≤
V
IN
≤
5.5V — — +/-100
µ
A
1. Insensitive to sequence of V
CC
and V
CCO
. However, assumes monotonic rise / fall rates for V
CC
and V
CCO
.
2. LVTTL, LVCMOS only
3. 0 < V
CC
≤
V
CC
(MAX), 0 < V
CCO
≤
V
CCO
(MAX)
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LC5768VG-12F256I

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Lattice
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CPLD - Complex Programmable Logic Devices PROGRAM EXPANDED LOG
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