Lattice Semiconductor ispMACH 5000VG Family Data Sheet
17
ispMACH 51024VG External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description
1,2,3
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
t
PD
Data propagation delay, 5-PT bypass — 5.0 — 7.5 — 10.0 — 12.0 ns
t
PD_PTSA
Data propagation delay, intrasegment path — 6.0 — 9.0 — 11.5 — 13.5 ns
t
PD_GLOBAL
Data propagation delay, intersegment path — 6.5 — 9.75 — 13.0 — 16.0 ns
t
S
GLB register setup time before clock,
5-PT bypass
3.0 — 5.0 — 7.5 — 9.3 — ns
t
S_PTSA
GLB register setup time before clock 3.0 — 6.0 — 8.5 — 10.0 — ns
t
SIR
GLB register setup time before clock, input
register path
2.8 — 3.0 — 4.0 — 5.0 — ns
t
H
GLB register hold time before clock, 5-PT
bypass
0.0 — 0.0 — 0.0 — 0.0 — ns
t
H_PTSA
GLB register hold time before clock 0.0 — 0.0 — 0.0 — 0.0 — ns
t
HIR
GLB register hold time before clock, input
reg. path
0.0 — 0.0 — 0.0 — 0.0 — ns
t
CO
GLB register clock-to-output delay — 4.4 — 5.0 — 6.0 — 7.0 ns
t
R
External reset pin to output delay — 6.5 — 9.0 — 10.0 — 10.9 ns
t
RW
External reset pulse duration 4.0 — 6.0 — 8.0 — 9.5 — ns
t
LPTOE/DIS
Input to output local product term output
enable/disable
— 7.0 — 9.75 — 11.5 — 13.4 ns
t
SPTOE/DIS
Input to output segment product term
output enable/disable
— 8.0 — 11.25 — 17.5 — 20.4 ns
t
GOE/DIS
Global OE input to output enable/disable — 6.2 — 7.5 — 8.85 — 10.0 ns
t
CW
Global clock width, high or low 1.6 — 2.75 — 3.6 — 4.3 — ns
t
GW
Global gate width low (for low transparent)
or high (for high transparent)
1.8 — 2.75 — 3.6 — 4.3 — ns
t
WIR
Input register clock width, high or low 1.8 — 2.75 — 3.6 — 4.3 — ns
t
SKEW
Clock-to-out skew, block level — 0.25 — 0.35 — 0.45 — 0.55 ns
Clock-to-out skew, segment level — 0.4 — 0.5 — 0.6 — 0.7 ns
f
MAX
4
Clock frequency with internal feedback 178.6 — 117.0 — 87.0 — 73.0 — MHz
f
MAX
(Ext.)
Clock frequency with external feedback,
1/ (t
S_PTSA
+ t
CO
)
135.1 — 90.9 — 69.0 — 58.8 — MHz
f
MAX
(Tog.) Clock frequency max Toggle 312.5 — 181.0 — 138.0 — 116.0 — MHz
Timing v.1.10
1. Timing numbers are based on default LVCMOS 3.3 I/O Buffers. Use timing adjusters provided to calculate timing for other standards.
2. Measured using standard switching circuit, assuming segment and global routing loading of 1, worst case PTSA loading and 1 output
switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using SRP feedback.
