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LC5768VG-12F256I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
19
ispMACH 5768VG Internal Timing Parameters
Over Recommended Operating Conditions
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
In/Out Delays
t
IN
Input Buffer Delay — 0.65 — 0.95 — 1.25 — 1.40 ns
t
GCLK_IN
Global Clock Input Buffer Delay — 0.65 — 0.95 — 1.25 — 1.40 ns
t
GOE
Global OE Pin Delay — 4.05 — 5.00 — 6.00 — 7.00 ns
t
BUF
Delay through Output Buffer — 1.15 — 1.50 — 1.75 — 1.90 ns
t
EN
Output Enable Time — 2.15 — 2.50 — 2.85 — 3.00 ns
t
DIS
Output Disable Time — 2.15 — 2.50 — 2.85 — 3.00 ns
t
RSTb
Global RESETbar Pin Delay — 4.60 — 6.50 — 7.00 — 7.50 ns
Routing Delays
t
ROUTE
Delay through SRP — 2.80 — 4.20 — 5.65 — 6.90 ns
t
PTSA
Product Term Sharing Array Delay — 0.40 — 1.85 — 2.35 — 2.50 ns
t
PDB
5-PT Bypass Propagation Delay — 0.40 — 0.85 — 1.35 — 1.80 ns
t
PDi
Macrocell Propagation Delay — 1.00 — 0.50 — 0.50 — 0.80 ns
t
INREG
Input Buffer to Macrocell Register Delay — 3.00 — 3.05 — 3.50 — 4.40 ns
t
FBK
Internal Feedback Delay — 0.00 — 0.00 — 0.00 — 0.00 ns
t
GCLK
Global Clock Tree Delay — 0.85 — 0.70 — 0.55 — 0.65 ns
t
PLL_DELAY
Programmable PLL Delay Increment — 0.50 — 0.50 — 0.50 — 0.50 ns
t
PLL_SEC_DELAY
Additional Delay When Using Secondary PLL
Output
— 0.60 — 0.60 — 0.60 — 0.60 ns
t
GRP
Global Routing Pool Delay — 1.50 — 2.25 — 3.00 — 4.00 ns
Register/Latch Delays
t
S
D-Register Setup Time 0.65 — 0.65 — 1.05 — 1.25 — ns
t
S_PT
D-Register Setup Time with PT Clock 0.65 — 0.65 — 1.05 — 1.25 — ns
t
H
D-Register Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
ST
T-Register Setup Time 1.15 — 1.15 — 1.55 — 1.75 — ns
t
ST_PT
T-Register Setup Time with PT Clock 1.15 — 1.15 — 1.55 — 1.75 — ns
t
HT
T-Register Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
COi
Register Clock to Output/Feedback MUX Time — 1.75 — 1.85 — 2.45 — 3.05 ns
t
CES
Clock Enable Setup Time 2.60 — 3.90 — 5.05 — 5.95 — ns
t
CEH
Clock Enable Hold Time 0.60 — 0.90 — 1.20 — 1.45 — ns
t
SL
Latch Setup Time 2.80 — 4.20 — 5.50 — 6.60 — ns
t
SL_PT
Latch Setup Time with PT Clock 2.80 — 4.20 — 5.50 — 6.60 — ns
t
HL
Latch Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
GOi
Latch Gate to Output/Feedback MUX Time — 1.75 — 2.50 — 3.50 — 4.50 ns
t
PDLi
Propagation Delay through Transparent Latch to
Output/Feedback MUX
— 2.40 — 3.50 — 4.00 — 4.50 ns
t
SRi
Asynchronous Reset or Set to Output/Feedback
MUX Delay
— 0.75 — 1.00 — 1.25 — 1.50 ns
t
SRR
Asynchronous Reset or Set Recovery Delay — 1.00 — 1.50 — 2.00 — 2.50 ns
Control Delays
t
BCLK
GLB PT Clock Delay — 3.10 — 4.65 — 6.00 — 7.00 ns
t
PTCLK
Macrocell PT Clock Delay — 3.00 — 4.50 — 6.00 — 7.00 ns
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
20
t
BSR
Block PT Set/Reset Delay — 2.00 — 3.00 — 4.00 — 4.80 ns
t
PTSR
Macrocell PT Set/Reset Delay — 2.00 — 3.00 — 4.00 — 4.80 ns
t
SPTOE
Segment PT OE Delay — 2.40 — 3.60 — 7.75 — 9.10 ns
t
PTOE
Macrocell PT OE Delay — 1.40 — 2.10 — 1.75 — 2.10 ns
Notes: Timing v.1.20
1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
2. t
PLL_DELAY
is the unit increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to 3.5ns in either
direction in units of 0.5ns for each step.
ispMACH 51024VG Internal Timing Parameters
Over Recommended Operating Conditions
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
In/Out Delays
t
IN
Input Buffer Delay — 0.65 — 0.95 — 1.25 — 1.40 ns
t
GCLK_IN
Global Clock Input Buffer Delay — 0.65 — 0.95 — 1.25 — 1.40 ns
t
GOE
Global OE Pin Delay — 4.05 — 5.00 — 6.00 — 7.00 ns
t
BUF
Delay through Output Buffer — 1.15 — 1.50 — 1.75 — 1.90 ns
t
EN
Output Enable Time — 2.15 — 2.50 — 2.85 — 3.00 ns
t
DIS
Output Disable Time — 2.15 — 2.50 — 2.85 — 3.00 ns
t
RSTb
Global RESETbar Pin Delay — 4.60 — 6.50 — 7.00 — 7.50 ns
Routing Delays
t
ROUTE
Delay through SRP — 2.80 — 4.20 — 5.65 — 6.90 ns
t
PTSA
Product Term Sharing Array Delay — 0.40 — 1.85 — 2.35 — 2.50 ns
t
PDB
5-PT Bypass Propagation Delay — 0.40 — 0.85 — 1.35 — 1.80 ns
t
PDi
Macrocell Propagation Delay — 1.00 — 0.50 — 0.50 — 0.80 ns
t
INREG
Input Buffer to Macrocell Register Delay — 3.00 — 3.05 — 3.50 — 4.40 ns
t
FBK
Internal Feedback Delay — 0.00 — 0.00 — 0.00 — 0.00 ns
t
GCLK
Global Clock Tree Delay — 0.85 — 0.70 — 0.55 — 0.65 ns
t
PLL_DELAY
Programmable PLL Delay Increment — 0.50 — 0.50 — 0.50 — 0.50 ns
t
PLL_SEC_DELAY
Additional Delay When Using Secondary PLL
Output
— 0.60 — 0.60 — 0.60 — 0.60 ns
t
GRP
Global Routing Pool Delay — 1.50 — 2.25 — 3.00 — 4.00 ns
Register/Latch Delays
t
S
D-Register Setup Time 0.65 — 0.65 — 1.05 — 1.25 — ns
t
S_PT
D-Register Setup Time with PT Clock 0.65 — 0.65 — 1.05 — 1.25 — ns
t
H
D-Register Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
ST
T-Register Setup Time 1.15 — 1.15 — 1.55 — 1.75 — ns
t
ST_PT
T-Register Setup Time with PT Clock 1.15 — 1.15 — 1.55 — 1.75 — ns
t
HT
T-Register Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
COi
Register Clock to Output/Feedback MUX Time — 1.75 — 1.85 — 2.45 — 3.05 ns
ispMACH 5768VG Internal Timing Parameters (Continued)
Over Recommended Operating Conditions
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
21
t
CES
Clock Enable Setup Time 2.60 — 3.90 — 5.05 — 5.95 — ns
t
CEH
Clock Enable Hold Time 0.60 — 0.90 — 1.20 — 1.45 — ns
t
SL
Latch Setup Time 2.80 — 4.20 — 5.50 — 6.60 — ns
t
SL_PT
Latch Setup Time with PT Clock 2.80 — 4.20 — 5.50 — 6.60 — ns
t
HL
Latch Hold Time 0.00 — 0.00 — 0.00 — 0.00 — ns
t
GOi
Latch Gate to Output/Feedback MUX Time — 1.75 — 2.50 — 3.50 — 4.50 ns
t
PDLi
Propagation Delay through Transparent Latch to
Output/Feedback MUX
— 2.40 — 3.50 — 4.00 — 4.50 ns
t
SRi
Asynchronous Reset or Set to Output/Feedback
MUX Delay
— 0.75 — 1.00 — 1.25 — 1.50 ns
t
SRR
Asynchronous Reset or Set Recovery Delay — 1.00 — 1.50 — 2.00 — 2.50 ns
Control Delays
t
BCLK
GLB PT Clock Delay — 3.10 — 4.65 — 6.00 — 7.00 ns
t
PTCLK
Macrocell PT Clock Delay — 3.00 — 4.50 — 6.00 — 7.00 ns
t
BSR
Block PT Set/Reset Delay — 2.00 — 3.00 — 4.00 — 4.80 ns
t
PTSR
Macrocell PT Set/Reset Delay — 2.00 — 3.00 — 4.00 — 4.80 ns
t
SPTOE
Segment PT OE Delay — 2.40 — 3.60 — 7.75 — 9.10 ns
t
PTOE
Macrocell PT OE Delay — 1.40 — 2.10 — 1.75 — 2.10 ns
Notes: Timing v.1.10
1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
2. t
PLL_DELAY
is the unit increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to 3.5ns in either
direction in units of 0.5ns for each step.
ispMACH 51024VG Internal Timing Parameters (Continued)
Over Recommended Operating Conditions
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

LC5768VG-12F256I

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Buy LC5768VG-12F256I
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Lattice
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CPLD - Complex Programmable Logic Devices PROGRAM EXPANDED LOG
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