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LC5768VG-12F256I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
22
ispMACH 5768VG Timing Adders
Adder
Type
Base
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
t
BLA
t
ROUTE
GLB Loading Adder — 0.0 — 0.0 — 0.0 — 0.0 ns
t
EXP
t
PTSA
PT Expander Adder — 1.5 — 2.0 — 2.5 — 2.5 ns
t
LP
t
ROUTE
Low Power Adder — 1.5 — 1.5 — 1.5 — 1.5 ns
t
IOI
Input Adders
LVCMOS18_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS1.8
standard
— 0.90 — 0.90 — 0.90 — 0.90 ns
LVCMOS25_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS2.5
standard
— 0.15 — 0.15 — 0.15 — 0.15 ns
LVCMOS33_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS3.3
standard
—0.0—0.0—0.0 — 0.0 ns
LVTTL
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVTTL standard — 0.0 — 0.0 — 0.0 — 0.0 ns
PCI_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using PCI standard — 0.0 — 0.0 — 0.0 — 0.0 ns
PCI_X_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using PCI_X
standard
—0.0—0.0—0.0 — 0.0 ns
AGP_1X_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using AGP-1X
standard
—0.0—0.0—0.0 — 0.0 ns
SSTL3_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL3_I
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL3_II_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL3_II
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL2_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL2_I
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL2_II_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL2_II
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
CTT33_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using CTT3.3
standard
—0.0—0.0—0.0 — 0.0 ns
CTT25_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using CTT2.5
standard
— 0.15 — 0.15 — 0.15 — 0.15 ns
HSTL_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using HSTL_I
standard
— 1.25 — 1.25 — 1.25 — 1.25 ns
HSTL_III_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using HSTL_III
standard
— 1.25 — 1.25 — 1.25 — 1.25 ns
GTL+_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using GTL+
standard
— 1.50 — 1.50 — 1.50 — 1.50 ns
LVDS_in t
GCLK_IN
Using LVDS
standard
— 1.70 — 1.70 — 1.70 — 1.70 ns
LVPECL_in t
GCLK_IN
Using LVPECL
standard
— 2.10 — 2.10 — 2.10 — 2.10 ns
t
IOO
Output Adders
LVCMOS18_4mA_out t
BUF
, t
EN
, t
DIS
Output configured as
1.8V & 4mA Buffer
— 3.00 — 3.00 — 3.00 — 3.00 ns
LVCMOS18_5mA_out t
BUF
, t
EN
, t
DIS
Output configured as
1.8V & 5.33mA Buffer
— 2.50 — 2.50 — 2.50 — 2.50 ns
LVCMOS18_8mA_out t
BUF
, t
EN
, t
DIS
Output configured as
1.8V & 8mA Buffer
— 1.85 — 1.85 — 1.85 — 1.85 ns
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.20
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
23
LVCMOS18_12mA_out t
BUF
, t
EN
, t
DIS
Output configured as
1.8V & 12mA Buffer
— 1.35 — 1.35 — 1.35 — 1.35 ns
LVCMOS25_4mA_out t
BUF
, t
EN
, t
DIS
Output configured as
2.5V & 4mA Buffer
— 1.50 — 1.50 — 1.50 — 1.50 ns
LVCMOS25_5mA_out t
BUF
, t
EN
, t
DIS
Output configured as
2.5V & 5.33mA Buffer
— 1.25 — 1.25 — 1.25 — 1.25 ns
LVCMOS25_8mA_out t
BUF
, t
EN
, t
DIS
Output configured as
2.5V & 8mA Buffer
— 0.70 — 0.70 — 0.70 — 0.70 ns
LVCMOS25_12mA_out t
BUF
, t
EN
, t
DIS
Output configured as
2.5V & 12mA Buffer
— 0.50 — 0.50 — 0.50 — 0.50 ns
LVCMOS25_16mA_out t
BUF
, t
EN
, t
DIS
Output configured as
2.5V & 16mA Buffer
— 0.25 — 0.25 — 0.25 — 0.25 ns
LVCMOS33_4mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 4mA Buffer
— 1.50 — 1.50 — 1.50 — 1.50 ns
LVCMOS33_5mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 5.33mA Buffer
— 1.25 — 1.25 — 1.25 — 1.25 ns
LVCMOS33_8mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 8mA Buffer
— 0.40 — 0.40 — 0.40 — 0.40 ns
LVCMOS33_12mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 12mA Buffer
— 0.10 — 0.10 — 0.10 — 0.10 ns
LVCMOS33_16mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 16mA Buffer
—0.0—0.0—0.0 — 0.0 ns
LVCMOS33_20mA_out t
BUF
, t
EN
, t
DIS
Output configured as
3.3V & 20mA Buffer
—0.0—0.0—0.0 — 0.0 ns
LVTTL t
BUF
, t
EN
, t
DIS
Output configured as
LVTTL Buffer
—0.0—0.0—0.0 — 0.0 ns
Slow Slew t
BUF
, t
EN
Output configured for
slow slew rate
— 1.50 — 1.50 — 1.50 — 1.50 ns
PCI_out t
BUF
, t
EN
, t
DIS
Using PCI standard — 0.0 — 0.0 — 0.0 — 0.0 ns
PCI_X_out t
BUF
, t
EN
, t
DIS
Using PCI-X
standard
—0.0—0.0—0.0 — 0.0 ns
AGP_1X_out t
BUF
, t
EN
, t
DIS
Using AGP-1X
standard
—0.0—0.0—0.0 — 0.0 ns
SSTL3_I_out t
BUF
, t
EN
, t
DIS
Using SSTL3_I
standard
— -0.25 — -0.25 — -0.25 — -0.25 ns
SSTL3_II_out t
BUF
, t
EN
, t
DIS
Using SSTL3_II
standard
— -0.35 — -0.35 — -0.35 — -0.35 ns
SSTL2_I_out t
BUF
, t
EN
, t
DIS
Using SSTL2_I
standard
—0.0—0.0—0.0 — 0.0 ns
SSTL2_II_out t
BUF
, t
EN
, t
DIS
Using SSTL2_II
standard
— -0.25 — -0.25 — -0.25 — -0.25 ns
CTT33_out t
BUF
, t
EN
, t
DIS
Using CCT3.3
standard
—0.0—0.0—0.0 — 0.0 ns
CTT25_out t
BUF
, t
EN
, t
DIS
Using CCT2.5
standard
— 0.25 — 0.25 — 0.25 — 0.25 ns
HSTL_I_out t
BUF
, t
EN
, t
DIS
Using HSTL_I
standard
— -0.30 — -0.30 — -0.30 — -0.30 ns
ispMACH 5768VG Timing Adders (Continued)
Adder
Type
Base
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.20
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
24
HSTL_III_out t
BUF
, t
EN
, t
DIS
Using HSTL_III
standard
— 0.00 — 0.00 — 0.00 — 0.00 ns
GTL+_out t
BUF
, t
EN
, t
DIS
Using GTL+
standard
— 0.30 — 0.30 — 0.30 — 0.30 ns
ispMACH 51024VG Timing Adders
Adder
Type
Base
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
t
BLA
t
ROUTE
GLB Loading Adder — 0.0 — 0.0 — 0.0 — 0.0 ns
t
EXP
t
PTSA
PT Expander Adder — 1.5 — 2.0 — 2.5 — 2.5 ns
t
LP
t
ROUTE
Low Power Adder — 1.5 — 1.5 — 1.5 — 1.5 ns
t
IOI
Input Adders
LVCMOS18_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS1.8
standard
— 0.90 — 0.90 — 0.90 — 0.90 ns
LVCMOS25_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS2.5
standard
— 0.15 — 0.15 — 0.15 — 0.15 ns
LVCMOS33_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVCMOS3.3
standard
—0.0—0.0—0.0 — 0.0 ns
LVTTL
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using LVTTL standard — 0.0 — 0.0 — 0.0 — 0.0 ns
PCI_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using PCI standard — 0.0 — 0.0 — 0.0 — 0.0 ns
PCI_X_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using PCI_X
standard
—0.0—0.0—0.0 — 0.0 ns
AGP_1X_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using AGP-1X
standard
—0.0—0.0—0.0 — 0.0 ns
SSTL3_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL3_I
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL3_II_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL3_II
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL2_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL2_I
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
SSTL2_II_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using SSTL2_II
standard
— 1.00 — 1.00 — 1.00 — 1.00 ns
CTT33_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using CTT3.3
standard
—0.0—0.0—0.0 — 0.0 ns
CTT25_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using CTT2.5
standard
— 0.15 — 0.15 — 0.15 — 0.15 ns
HSTL_I_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using HSTL_I
standard
— 1.25 — 1.25 — 1.25 — 1.25 ns
HSTL_III_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using HSTL_III
standard
— 1.25 — 1.25 — 1.25 — 1.25 ns
GTL+_in
t
IN
, t
GCLK_IN
,
t
RSTb
, t
GOE
Using GTL+
standard
— 1.50 — 1.50 — 1.50 — 1.50 ns
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.10
ispMACH 5768VG Timing Adders (Continued)
Adder
Type
Base
Parameter Description
-5 -75 -10 -12
UnitsMin Max Min Max Min Max Min Max
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

LC5768VG-12F256I

Mfr. #:
Buy LC5768VG-12F256I
Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices PROGRAM EXPANDED LOG
Lifecycle:
New from this manufacturer.
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