Lattice Semiconductor ispMACH 5000VG Family Data Sheet
27
sysCLOCK PLL Timing
Over Recommended Operating Conditions
1
Boundary Scan Timing Specifications
Symbol Parameter Conditions Min Max Units
t
R
,t
F
Input clock, rise and fall time 20% to 80% — 3.0 ns
t
INSTB
Input clock stability, period jitter (peak)
1
——+/- 200 ps
t
PWH
Input clock, high time — 1.6 — ns
t
PWL
Input clock, low time — 1.6 — ns
f
MDIVIN
M Divider input, frequency range — 5 180 MHz
f
MDIVOUT
M Divider output, frequency range — 5 180 MHz
f
VDIVIN
V Divider input, frequency range — 60 200 MHz
f
VDIVOUT
V Divider output, frequency range — 5 180 MHz
t
OUTDUTY
Output clock, duty cycle — 40 60 %
t
JIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean Reference,
5MHz ≤ f
MDIVOUT
< 80MHz
— +/- 200 ps
Clean Reference,
80MHz ≤ f
MDIVOUT
≤ 180MHz
— +/- 100 ps
t
JIT(φ)
Output clock, accumulated phase jitter (peak)
2
Clean Reference,
5MHz ≤ f
MDIVOUT
< 80MHz
— +/- 200 ps
Clean Reference,
80MHz ≤ f
MDIVOUT
≤ 180MHz
— +/- 100 ps
t
CLK_OUT_DLY
Input clock to CLK_OUT delay Internal feedback — 1 ns
t
φ
Input clock to external feedback delta External feedback — 500 ps
t
LOCK
Time to acquire phase lock after input stable — — 30 µs
t
PLL_DELAY
Delay increment — +/- 0.35 +/- 0.65 ns
t
RANGE
Total output delay range — +/- 2.45 +/- 4.55 ns
t
PLL_RSTR
Reset recovery time of the M-divider — 11.0 — ns
t
PLL_RSTW
Minimum reset pulse width — 6.0 — ns
1. This condition assures that the output phase jitter (t
JIT(φ)
) will remain within specification.
2. Accumulated jitter measured over 10,000 waveform samples.
Symbol Parameter Min. Max. Units
t
BTCP
TCK [BSCAN test] clock cycle 40 — ns
t
BTCH
TCK [BSCAN test] pulse width high 20 — ns
t
BTCL
TCK [BSCAN test] pulse width low 20 — ns
t
BTSU
TCK [BSCAN test] setup time 8 — ns
t
BTH
TCK [BSCAN test] hold time 10 — ns
t
BRF
TCK [BSCAN test] rise and fall time 50 — mV/ns
t
BTCO
TAP controller falling edge of clock to valid output — 10 ns
t
BTOZ
TAP controller falling edge of clock to data output disable — 10 ns
t
BTVO
TAP controller falling edge of clock to data output enable — 10 ns
t
BVTCPSU
BSCAN test Capture register setup time 8 — ns
t
BTCPH
BSCAN test Capture register hold time 10 — ns
t
BTUCO
BSCAN test Update reg, falling edge of clock to valid output — 25 ns
t
BTUOZ
BSCAN test Update reg, falling edge of clock to output disable — 25 ns
t
BTUOV
BSCAN test Update reg, falling edge of clock to output enable — 25 ns
