Lattice Semiconductor ispMACH 5000VG Family Data Sheet
4
ing with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control prod-
uct terms, the rst, third, fourth and fth product terms of each cluster can be used as a PTOE (output macrocells
only), PT Clock, PT Preset and PT Reset, respectively. Figure 4 is a graphical representation of the AND-Array.
Figure 3. Macrocell Slice
Figure 4. AND-Array
From
SRP
68
Speed/
Power
PTSA
From
n-7
To
n+7
PTSA Bypass
PT OE to
I/O Block
From
I/O Cell
PT Clock
PT Preset
PT Reset
Shared PT Reset
Shared PT Clock
BCLK0
BCLK1
BCLK2
BCLK3
Global Reset
Clk En
Clk
R/L
D
PR
Q
AND Array Dual-OR Array Macrocell
Output
to I/O Block
GRP and SRP
PT0
PT1
Cluster 0
PT2
PT3
PT4
In[0]
In[66]
In[67]
Note:
Indicates programmable fuse.
PT160
PT161
PT162
Shared cloc
k
Shared reset
Shared OE
PT156
PT157
PT158
PT159
PT155
Cluster 31
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
5
Enhanced Dual-OR Array
To facilitate logic functions requiring a very large number of product terms, the ispMACH 5000VG architecture has
been enhanced with an innovative product term expander capability. This capability is embedded in the Dual-OR
Array. The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the GLB. These OR
gates are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate.
The PTSA-Bypass OR gate receives its ve inputs from the combination of product terms associated with the prod-
uct term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable
PTSA OR gate receives ve inputs from the combination of product terms associated with the product term cluster.
It also receives an additional input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number
of the macrocell associated with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing
with other product terms and the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for
wide functions. There is a small timing adder for each level of expansion. Figure 5 is a graphical representation of
the Enhanced Dual-OR Array.
Figure 5. Enhanced Dual-OR Array
From
n-7
To
n+7
From PT0
From PT1
From PT2
From PT3
From PT4
PTSA Bypass
To Macrocell
To I/O Block
To Macrocell
To Macrocell
To Macrocell
To PTSA
PT OE
PT Clock
PT Preset
PT Reset
n
Lattice Semiconductor ispMACH 5000VG Family Data Sheet
6
Product Term Sharing Array
The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and
32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven Expandable
PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2 and
N+3 PTSA OR terms via a programmable connection. This wraps around the logic, Macrocell 0 gets its logic from
29, 30, 31, 0, 1, 2, 3. The Expandable PTSA OR used in conjunction with the PTSA allows wide functions to be
implemented easily and efciently. Without using the Expandable PTSA OR capability, the greatest number of
product terms that can be included in a single function with one pass of delay is 35. Figure 6 shows the graphical
representation of the PTSA.
Macrocell
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch ip-op and the necessary clocks
and control logic to allow combinatorial or registered operation.
The macrocells each have two outputs, which can be fed to the SRP, GRP and I/O cell. This dual or concurrent out-
put capability from the macrocell gives efcient use of the hardware resources. One output can be a registered
function for example, while the other output can be an unrelated combinatorial function. A direct register input from
the I/O cell facilitates efcient use of the macrocell to construct high-speed input registers.
Macrocell registers can be clocked from one of several global or product term clocks available on the device. A glo-
bal and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers
directly. Reset and preset for the macrocell register is provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 7 is a graphical rep-
resentation of the ispMACH 5000VG macrocell.
Figure 6. Product Term Sharing Array
PTSA OR 0
PTSA OR 1
PTSA OR 2
PTSA OR 3
PTSA OR 29
PTSA OR 30
PTSA OR 31
Macrocell 0
Macrocell 1
Macrocell 2
Macrocell 29
Macrocell 30
Macrocell 31

LC5768VG-12F256I

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Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices PROGRAM EXPANDED LOG
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