Lattice Semiconductor ispMACH 5000VG Family Data Sheet
30
Signal Descriptions
Signal Names Description
TMS Input - This pin is the Test Mode Select input, which is used to control the 1149.1 state machine.
TCK Input - This pin is the Test Clock input pin, used to clock the 1149.1 state machine.
TDI Input - This pin is the 1149.1 Test Data In pin, used to load data.
TDO Output - This pin is the 1149.1 Test Data Out pin used to shift data out.
TOE Input - Test Output Enable pin. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1 Input - These two pins are the Global Output Enable input pins.
RESETB
Dedicated Reset Input - This pin resets all registers in the devices. The global polarity (active high or
low input) for this pin is selectable.
xyzz (e.g. 0A16)
Input/Output - These are the general purpose I/O used by the logic array.
x is segment reference
(numeric),
y is GLB reference (alpha) and z is macrocell reference (numeric).
x: 0-7 (1024)
x: 0-5 (768)
y: A-D
z: 0-31
GND Ground
NC No connect
V
CC
Vcc - These are the power supply pins for the logic core.
GCLK0, GCLK3 Input - These pins are configured to be either dedicated CLK input or PLL input.
GCLK1, GCLK2 Input - These pins are dedicated CLK input.
CLK_OUT0,
CLK_OUT1
Output - These pins are the PLL output pins.
PLL_RST0,
PLL_RST1
Input - These pins are for resetting the PLL, input clock (M) divider.
VREF0, VREF1,
VREF2, VREF3
Input - These are the reference supplies for the I/O banks.
PLL_FBK0,
PLL_FBK1
Input - These PLL feedback inputs allow optional external PLL feedback.
V
CCP0
, V
CCP1
V
CC
- These are the V
CC
supplies for the PLLs.
V
CCO0
, V
CCO1
, V
CCO2
,
V
CCO3
V
CC
- These are the V
CC
supplies for each I/O bank.
GNDP0, GNDP1 GND - These are the separate ground connections for the PLLs.
V
CCJ
V
CC
- This pin is for the 1149.1 test access port.
Note: For above, signal CLK_OUT0 connects to PLL0, and signal CLK_OUT1 connects to PLL1.
