Lattice Semiconductor ispMACH 5000VG Family Data Sheet
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Global clock pins have additional capabilities that allow for higher performance applications. Two global clock pins
can be paired together to create a single global clock pin that can interface with certain differential signals.
The TOE and JTAG pins of the ispMACH 5000VG device are the only pins that do not have sysIO capabilities.
These pins only support the LVTTL and LVCMOS standards.
There are three classes of I/O interface standards that are implemented in the ispMACH 5000VG devices. The first
is the unterminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V
LVCMOS interface standards. Additionally, PCI 3.3, PCI-X and AGP-1X are all subsets of this type of interface.
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT and GTL+. Usage of these particular
I/O interfaces requires the use of an additional VREF signal. At the system level, a termination voltage, VTT, is also
required. Typically, an output will be terminated to VTT at the receiving end of the transmission line it is driving.
The final types of interfaces implemented are the differential standards LVDS and LVPECL. These interfaces are
implemented on clock pins only. When using one of the differential standards, a pair of global clock pins (GCLK0
and GCLK1 or GCLK3 and GCLK2) is combined to create a single clock signal.
For more information on the sysIO capability, please refer to Technical Note TN1000:
ispMACH 5000VG sysIO
Design and Usage Guidelines
.
GLB Clock Distribution
The ispMACH 5000VG family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be
routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are
directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK cir-
cuit). These feed the GLB clock multiplexes which generate the GLB clock signals (BCLK0-BCLK3). The GLB clock
multiplexer allows a variety of true and complementary versions of the clocks to be used within the GLB. Each
block clock can be the true or inverse of its associated global clock or the inverse of the adjacent global clock.
Figure 9 shows the clock distribution network.
Figure 9. Clock Distribution Network
sysCLOCK PLLs Global Clock Routing GLB Clock Routing
Clock Net
PLL0
CLK_OUT0
SEC_OUT0
VREF0
CLK0
CLK1
GCLK0
GCLK1
I/O/CLK_OUT0
Clock Net
Clock Net
PLL1
CLK_OUT1
SEC_OUT1
CLK3
CLK2
GCLK3
GCLK2
I/O/CLK_OUT1
Clock Net
BCLK0
BCLK1
BCLK2
BCLK3
To Macrocells
To Macrocells
To Macrocells
To Macrocells
VREF1
VREF3
VREF2
