NXP Semiconductors
SL2S2002_SL2S2102
ICODE SLIX
SL2S2002_SL2S2102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet Rev. 3.4 — 10 August 2017
COMPANY PUBLIC 178034 30 / 39
14 Bare die outline
001aam108
not to scale!
(1)
(7)
(2)
(8)
(5)
(6)
(4)
(3)
Y
X
GND
LA LB
TEST
(1) X-scribe line width: 15 μm
(2) Y-scribe line width: 15 μm
(3) Chip step, X-length: 535 μm
(4) Chip step, Y-length: 499 μm
(5) Bump to bump distance X (LA - LB): 400 μm
(6) Bump to bump distance Y (LB - TEST): 360 μm
(7) Distance bump to nitride edge X: 75 μm
(8) Distance bump to nitride edge Y: 45 μm
Bump size X × Y: 60 μm × 60 μm
Figure 8. Wafer SL2S2002FUDbare die layout