NXP Semiconductors
SL2S2002_SL2S2102
ICODE SLIX
SL2S2002_SL2S2102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet Rev. 3.4 — 10 August 2017
COMPANY PUBLIC 178034 9 / 39
8 Mechanical specification
8.1 Wafer specification
See Ref. 6 "General specification for 8" wafer on UV-tape with electronic fail die
marking".
Table 5. Wafer specification
Wafer
Designation each wafer is enscribed with batch number and wafer number
Diameter 200 mm (8 inches)
Thickness 120 μm ± 15 μm
Process CMOS 0.14 μm
Batch size 25 wafers
Dies per wafer
SL2S2002FUD 110050
SL2S2102FUD 88225
Wafer backside
Material Si
Treatment ground and stress release
R
a
minimum = 0.5 μmRoughness
R
t
maximum = 5 μm
Chip dimensions
Die size without scribe
SL2S2002FUD 520 μm × 484 μm = 251680 μm
2
SL2S2102FUD 520 μm × 607 μm = 315640 μm
2
Scribe line width
X-dimension 15 μm (scribe line width measured between nitride edges)
Y-dimension 15 μm (scribe line width measured between nitride edges)
Number of pads 4
Pad location non-diagonal/placed in chip corners
Distance pad to pad LA to LB 400 μm
Distance pad to pad LB to TEST
SL2S2002FUD 360 μm
SL2S2102FUD 517 μm
Passivation on front
Type sandwich structure
Material PE-nitride (on top)
Thickness 1.75 μm total thickness of passivation
