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SC68C752BIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 10 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
There are two other enhanced features relating to software flow control:
• Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
6.3.1 Receive flow control
When software flow control operation is enabled, the SC68C752B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character are received, transmission is
halted after completing transmission of the current character. Xoff detection also sets
IIR[4] (if enabled via IER[5]) and causes IRQ
to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
6.3.2 Transmit flow control
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 7
shows an example of software flow control.
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 11 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.3.3 Software flow control example
6.3.3.1 Assumptions
UART1 is transmitting a large text file to UART2. Both UARTs are using software flow
control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold
(TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the
interrupt receive threshold (TLR[7:4] = D) set to 52.
UART1 begins transmission and sends 52 characters, at which point UART2 will generate
an interrupt to its processor to service the RX FIFO, but assume the interrupt latency is
fairly long. UART1 will continue sending characters until a total of 60 characters have
been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt
transmission. UART1 will likely send the 61
st
character while UART2 is sending the Xoff
character. Now UART2 is serviced and the processor reads enough data out of the RX
FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1
to resume transmission.
Fig 7. Software flow control example
TRANSMIT FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
RECEIVE FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
UART2UART1
002aaa22
9
data
Xoff–Xon–Xoff
compare
programmed
Xon-Xoff
characters
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 12 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.4 Reset
Table 5 summarizes the state of register after reset.
Remark: Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the
top-level reset signal RESET
, that is, they hold their initialization values during reset.
Table 6
summarizes the state of registers after reset.
Table 5. Register reset functions
Register Reset control Reset state
Interrupt Enable Register RESET
all bits cleared
Interrupt Identification Register RESET
bit 0 is set; all other bits cleared
FIFO Control Register RESET
all bits cleared
Line Control Register RESET
reset to 0001 1101 (1Dh)
Modem Control Register RESET
all bits cleared
Line Status Register RESET
bits 5 and 6 set; all other bits cleared
Modem Status Register RESET
bits 0 to 3 cleared; bits 4 to 7 input signals
Enhanced Feature Register RESET
all bits cleared
Receiver Holding Register RESET
pointer logic cleared
Transmitter Holding Register RESET
pointer logic cleared
Transmission Control Register RESET
all bits cleared
Trigger Level Register RESET
all bits cleared
Table 6. Signal RESET functions
Signal Reset control Reset state
TXn RESET
HIGH
RTSn
RESET HIGH
DTRn
RESET HIGH
RXRDYn
RESET HIGH
TXRDYn
RESET LOW
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SC68C752BIBS,151

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Buy SC68C752BIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
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