SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 6 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
R/W 15 12 I A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an
external CPU to an internal register that is defined by address bits A[2:0]. A logic
HIGH on this pin will load the contents of an internal register defined by address
bits A[2:0] on the SC68C752B data bus (D[7:0]) for access by an external CPU.
n.c. 12, 25,
29, 37
14, 20 - not connected
OPA
32 22 O User defined outputs. This function is associated with individual Channel A and
Channel B. The state of these pins is defined by the user through the software
settings of MCR[3]. OPA/OPB is a logic 0 when MCR[3] is set to a logic 1.
OPA
/OPB is a logic 1 when MCR[3] is set to a logic 0. The output of these two
pins is HIGH after reset.
OPB
97 O
RESET
36 24 I Reset (active LOW). This pin will reset the internal registers and all the outputs.
The UART transmitter output and the receiver input will be disabled during reset
time. RESET
is an active LOW input.
RIA
41 - I Ring Indicator (active LOW). These inputs are associated with individual UART
Channel A and Channel B. A logic 0 on these pins indicates the modem has
received a ringing signal from the telephone line. A LOW-to-HIGH transition on
these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the Modem Status Register (MSR).
RIB
21 - I
RTSA
33 23 O Request to Send (active LOW). These outputs are associated with individual
UART Channel A and Channel B. A logic 0 on the RTSn pin indicates the
transmitter has data ready and waiting to send. Writing a logic 1 in the Modem
Control Register MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset these pins are set to a logic 1. These pins only affect the transmit
and receive operations when auto-RTS
function is enabled via the Enhanced
Feature Register (EFR[6]) for hardware flow control operation.
RTSB
22 16 O
RXA 5 4 I Receive data input. These inputs are associated with individual serial channel
data to the SC68C752B. During the local Loopback mode, these RXn input pins
are disabled and transmit data is connected to the UART receive input internally.
RXB 4 3 I
RXRDYA
31 - O Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the
trigger level has been reached or the FIFO has at least one character. It goes
HIGH when the receive FIFO is empty.
RXRDYB
18 - O
TXA 7 5 O Transmit data A, B. These outputs are associated with individual serial transmit
channel data from the SC68C752B. During the local Loopback mode, the TXn
output pin is disabled and transmit data is internally connected to the UART
receive input.
TXB 8 6 O
TXRDYA
43 - O Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are at
least a trigger level number of spaces available or when the FIFO is empty. It
goes HIGH when the FIFO is full or not empty.
TXRDYB
6- O
V
CC
19, 42 26 I Power supply input.
XTAL1 13 10 I Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between XTAL1 and XTAL2 to form an
internal oscillator circuit (see Figure 13
). Alternatively, an external clock can be
connected to this pin to provide custom data rates.
XTAL2 14 11 O Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is
used as a crystal oscillator output or a buffered clock output.
Table 2. Pin description
…continued
Symbol Pin Type Description
LQFP48 HVQFN32
