OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SC68C752BIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 28 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 18
shows Interrupt Identification Register bit settings.
The interrupt priority list is shown in Table 19.
Table 18. Interrupt Identification Register bits description
Bit Symbol Description
7:6 IIR[7:6] Mirror the contents of FCR[0].
5 IIR[5] RTSn
/CTSn LOW-to-HIGH change of state
4 IIR[4] 1 = Xoff/Special character has been detected
3:1 IIR[3:1] 3-bit encoded interrupt. See Table 19
.
0 IIR[0] Interrupt status.
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Table 19. Interrupt priority list
Priority
level
IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt
1 000110receiver line status error
2 001100receiver time-out interrupt
2 000100RHR interrupt
3 000010THR interrupt
4 000000modem interrupt
5 010000received Xoff signal/ special
character
6 100000CTSn
, RTSn change of state from
active (LOW) to inactive (HIGH)
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 29 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 20
shows the Enhanced Feature Register bit settings.
7.11 Divisor latches (DLL, DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLM can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
7.12 Transmission Control Register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to stop/start
transmission during hardware/software flow control. Table 21
shows transmission control
register bit settings.
TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.
Table 20. Enhanced Feature Register bits description
Bit Symbol Description
7 EFR[7] CTS
flow control enable.
logic 0 = CTS
flow control is disabled (normal default condition)
logic 1 = CTS
flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTSn
pin.
6EFR[6]RTS
flow control enable.
logic 0 = RTS
flow control is disabled (normal default condition)
logic 1 = RTS
flow control is enabled. The RTSn pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the
receiver FIFO resume transmission trigger level TCR[7:4] is reached.
5 EFR[5] Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logic 1 to indicate a special character has been detected.
4 EFR[4] Enhanced functions enable bit.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5]
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
can be modified, that is, this bit is therefore a write enable
3:0 EFR[3:0] Combinations of software flow control can be selected by programming these
bits. See Table 4 “
Software flow control options (EFR[3:0])” on page 9.
Table 21. Transmission Control Register bits description
Bit Symbol Description
7:4 TCR[7:4] receive FIFO trigger level to resume transmission (0 bytes to 60 bytes).
3:0 TCR[3:0] receive FIFO trigger level to halt transmission (0 bytes to 60 bytes).
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 30 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before auto-RTS
or software flow control is enabled to avoid spurious operation
of the device.
7.13 Trigger Level Register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4. Table 22
shows trigger level register bit settings.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logic 0, the selectable trigger levels via the FIFO control register (FCR) are
used for the transmit and receive FIFO trigger levels. Trigger levels from
4 bytes to 60 bytes are available with a granularity of four. The TLR should be
programmed for
N
⁄
4
, where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting
defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is
discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
that is, ‘00’.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CS
= 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is
disabled. The address is 111.
Table 22. Trigger Level Register bits description
Bit Symbol Description
7:4 TLR[7:4] receive FIFO trigger levels (4 to 60), number of characters available.
3:0 TLR[3:0] transmit FIFO trigger levels (4 to 60), number of spaces available.
Table 23. FIFO ready register bits description
Bit Symbol Description
7:6 FIFO Rdy[7:6] unused; always 0
5 FIFO Rdy[5] receive FIFO B status; related to DMA
4 FIFO Rdy[4] receive FIFO A status; related to DMA
3:2 FIFO Rdy[3:2] unused; always 0
1 FIFO Rdy[1] transmit FIFO B status; related to DMA
0 FIFO Rdy[0] transmit FIFO A status; related to DMA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC68C752BIBS,151

Mfr. #:
Buy SC68C752BIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet