SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 17 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RXn, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TXn line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generator
The SC68C752B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2
16
− 1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 12
. The output frequency of the baud rate generator is 16 times the baud rate. The
formula for the divisor is:
(1)
Where:
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 12
shows the internal prescaler and baud rate generator circuitry.
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least significant and most significant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 8
and Table 9 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 13
shows the crystal clock circuit reference.
Fig 12. Prescaler and baud rate generator block diagram
divisor
XTAL1 crystal input frequency
prescaler
-----------------------------------------------------------------------------------
⎝⎠
⎛⎞
desired baud rate 16×
-----------------------------------------------------------------------------------------
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
