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SC68C752BIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 31 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
8. Programmer’s guide
The base set of registers that is used during high-speed data transfer have a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.
Table 24. Register programming guide
Command Actions
Set baud rate to VALUE1, VALUE2 read LCR (03h), save in temp
set LCR (03h) to 80h
set DLL (00h) to VALUE1
set DLM (01h) to VALUE2
set LCR (03h) to temp
Set Xoff1, Xon1 to VALUE1, VALUE2 read LCR (03h), save in temp
set LCR (03h) to BFh
set Xoff1 (06h) to VALUE1
set Xon1 (04h) to VALUE2
set LCR (03h) to temp
Set Xoff2, Xon2 to VALUE1, VALUE2 read LCR (03h), save in temp
set LCR (03h) to BFh
set Xoff2 (07h) to VALUE1
set Xon2 (05h) to VALUE2
set LCR (03h) to temp
Set software flow control mode to VALUE read LCR (03h), save in temp
set LCR (03h) to BFh
set EFR (02h) to VALUE
set LCR (03h) to temp
Set flow control threshold to VALUE read LCR (03h), save in temp1
set LCR (03h) to BFh
read EFR (02h), save in temp2
set EFR (02h) to 10h + temp2
set LCR (03h) to 00h
read MCR (04h), save in temp3
set MCR (04h) to 40h + temp3
set TCR (06h) to VALUE
set MCR (04h) to temp3
set LCR (03h) to BFh
set EFR (02h) to temp2
set LCR (03h) to temp1
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 32 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
[1] × sign here means bit-AND.
Set TX FIFO and RX FIFO thresholds
to VALUE
read LCR (03h), save in temp1
set LCR (03h) to BFh
read EFR (02h), save in temp2
set EFR (02h) to 10h + temp2
set LCR (03h) to 00h
read MCR (04h), save in temp3
set MCR (04h) to 40h + temp3
set TLR (07h) to VALUE
set MCR (04h) to temp3
set LCR (03h) to BFh
set EFR (02h) to temp2
set LCR (03h) to temp1
Read FIFO Rdy register read MCR (04h), save in temp1
set temp2 = temp1 × EFh
[1]
set MCR (04h) = 40h + temp2
read FFR (07h), save in temp2
pass temp2 back to host
set MCR (04h) to temp1
Set prescaler value to divide-by-1 read LCR (03h), save in temp1
set LCR (03h) to BFh
read EFR (02h), save in temp2
set EFR (02h) to 10h + temp2
set LCR (03h) to 00h
read MCR (04h), save in temp3
set MCR (04h) to temp3 × 7Fh
[1]
set LCR (03h) to BFh
set EFR (02h) to temp2
set LCR (03h) to temp1
Set prescaler value to divide-by-4 read LCR (03h), save in temp1
set LCR (03h) to BFh
read EFR (02h), save in temp2
set EFR (02h) to 10h + temp2
set LCR (03h) to 00h
read MCR (04h), save in temp3
set MCR (04h) to temp3 + 80h
set LCR (03h) to BFh
set EFR (02h) to temp2
set LCR (03h) to temp1
Table 24. Register programming guide
…continued
Command Actions
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 33 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
9. Limiting values
Table 25. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage - 7 V
V
n
voltage on any other pin at D7 to D0 GND − 0.3 V
CC
+0.3 V
at any input only pin GND − 0.3 5.3 V
V
O
output voltage −0.3 V
CC
+0.3 V
T
amb
ambient temperature operating in free-air −40 +85 °C
T
stg
storage temperature −65 +150 °C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC68C752BIBS,151

Mfr. #:
Buy SC68C752BIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
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