SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 25 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Remark: The three error bits (parity, framing, break) may not be updated correctly in the
first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz.
However, the second read is always correct. It is strongly recommended that when using
this device with a clock faster than 36 MHz, that the LSR be read twice and only the
second read be used for decision making. All other bits in the LSR are correct on all
reads.
7.6 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem. Table 15
shows Modem Control Register bit settings.
[1] MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
Table 15. Modem Control Register bits description
Bit Symbol Description
7 MCR[7]
[1]
Clock select.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6 MCR[6]
[1]
TCR and TLR enable.
logic 0 = no action.
logic 1 = enable access to the TCR and TLR registers
5 MCR[5]
[1]
Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
4 MCR[4] Enable loopback.
logic 0 = normal operating mode
logic 1 = Enable local Loopback mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TXn output is
looped back to the RXn input internally.
3 MCR[3] OPA
/OPB control.
logic 0 = forces OPA
/OPB output to HIGH state
logic 1 = forces OPA
/OPB output to LOW state. In Loopback mode,
controls MSR[7].
2 MCR[2] FIFO Ready enable.
logic 0 = Disable the FIFO Rdy register
logic 1 = Enable the FIFO Rdy register. In Loopback mode, controls
MSR[6].
1 MCR[1] RTS
logic 0 = force RTSn output to inactive (HIGH)
logic 1 = force RTSn
output to active (LOW). In Loopback mode,
controls MSR[4]. If auto-RTS is enabled, the RTSn output is controlled
by hardware flow control.
0 MCR[0] DTR
logic 0 = force DTRn output to inactive (HIGH)
logic 1 = force DTRn
output to active (LOW). In Loopback mode,
controls MSR[5].
