OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SC68C752BIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 19 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7. Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table 10
.
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7] is logic 1.
[4] Accessible only when LCR is set to 1011 1111 (BFh).
[5] Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
[6] Accessible only when CS
= 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
Fig 13. Crystal oscillator connections
002aaa87
0
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
Table 10. Register map - read/write properties
A2 A1 A0 Read mode Write mode
0 0 0 Receive Holding Register (RHR) Transmit Holding Register (THR)
0 0 1 Interrupt Enable Register (IER) Interrupt Enable Register
0 1 0 Interrupt Identification Register (IIR) FIFO Control Register (FCR)
0 1 1 Line Control Register (LCR) Line Control Register
1 0 0 Modem Control Register (MCR)
[1]
Modem Control Register
[1]
1 0 1 Line Status Register (LSR)
1 1 0 Modem Status Register (MSR)
1 1 1 ScratchPad Register (SPR) ScratchPad Register
0 0 0 Divisor Latch LSB (DLL)
[2][3]
divisor latch LSB
[2][3]
0 0 1 Divisor Latch MSB (DLM)
[2][3]
divisor latch MSB
[2][3]
0 1 0 Enhanced Feature Register (EFR)
[2][4]
Enhanced Feature Register
[2][4]
100Xon1 word
[2][4]
Xon1 word
[2][4]
101Xon2 word
[2][4]
Xon2 word
[2][4]
110Xoff1 word
[2][4]
Xoff1 word
[2][4]
111Xoff2 word
[2][4]
Xoff2 word
[2][4]
1 1 0 Transmission Control Register (TCR)
[2][5]
Transmission Control Register
[2][5]
1 1 1 Trigger Level Register (TLR)
[2][5]
Trigger Level Register
[2][5]
1 1 1 FIFO ready register
[2][6]
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 20 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 11 lists and describes the SC68C752B internal registers.
[1] These registers are accessible only when LCR[7] = 0.
[2] This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3] The Special register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced Feature Register; XON1/XON2 and XOFF1/XOFF2 are accessible only when LCR is set to ‘BFh’.
Table 11. SC68C752B internal registers
A2 A1 A0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read/
Write
General register set
[1]
0 0 0 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0 0 0 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W
001IER CTS
interrupt
enable
[2]
RTS
interrupt
enable
[2]
Xoff
[2]
Sleep
mode
[2]
modem
status
interrupt
receive
line status
interrupt
THR
empty
interrupt
RX data
available
interrupt
R/W
0 1 0 FCR RX trigger
level
(MSB)
RX trigger
level
(LSB)
TX trigger
level
(MSB)
[2]
TX trigger
level
(LSB)
[2]
DMA
mode
select
TX FIFO
reset
RX FIFO
reset
FIFO
enable
W
0 1 0 IIR FCR[0] FCR[0] CTS
,
RTS
Xoff interrupt
priority
bit 2
interrupt
priority
bit 1
interrupt
priority
bit 0
interrupt
status
R
011LCR DLAB break
control bit
set parity parity
type
select
parity
enable
number of
stop bits
word
length
bit 1
word
length
bit 0
R/W
100MCR 1× or 1×/4
clock
[2]
TCR and
TLR
enable
[2]
Xon
Any
[2]
enable
loopback
OPA/
OPB
control
FIFO
ready
enable
RTS DTR R/W
1 0 1 LSR error in
RX FIFO
THR and
TSR
empty
THR
empty
break
interrupt
framing
error
parity
error
overrun
error
data in
receiver
R
1 1 0 MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS R
1 1 1 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
111FIFO Rdy0 0 RX FIFO
B status
RX FIFO
A status
0 0 TX FIFO
B status
TX FIFO
A status
R
Special register set
[3]
0 0 0 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0 0 1 DLM bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
Enhanced register set
[4]
010EFR auto-CTSauto-RTS special
character
detect
enable
enhanced
functions
[2]
software
flow
control
bit 3
software
flow
control
bit 2
software
flow
control
bit 1
software
flow
control
bit 0
R/W
1 0 0 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 1 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 XOFF1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 XOFF2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
SC68C752B_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 20 January 2010 21 of 48
NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Remark: Refer to the notes under Table 10 for more register access information.
7.1 Receiver Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the line control register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC68C752BIBS,151

Mfr. #:
Buy SC68C752BIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet