TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 14 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
8.4.5 Clock protection (CP)
The clock signal can be provided by an external oscillator connected to pin OSC (see
Section 14.4). When this signal is lost, or the clock frequency is too low, the amplifier will
be switched off and will remain off until the clock signal has been restored.
8.4.6 Overview of protection functions
An overview of all protection circuits and their respective effects on the output signal is
provided in
Table 5.
[1] Amplifier gain depends on the junction temperature.
[2] TFB warning signal on pin DIAG1 is activated before TFB is enabled.
[3] The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold
(Z
th
; see Section 8.4.2). In all other cases, current limiting results in a clipped output signal.
[4] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been
activated (short-circuit to one of the supply lines).
[5] As soon as the clock is present.
8.5 Differential audio inputs
The audio inputs are fully differential ensuring a high common mode rejection ratio and
maximum flexibility in the application.
• Stereo operation: to avoid supply pumping effects and to minimize peak currents in
the power supply, the output stages should be configured in anti-phase. To avoid
acoustical phase differences, the speakers should also be connected in anti-phase.
• Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the
TDA8954. In practice (because of the OCP threshold) the maximum output power in
the BTL configuration can be boosted to twice the maximum output power available in
the single-ended configuration.
The input configuration for a mono BTL application is illustrated in Figure 10.
Table 5. Overview of TDA8954 protection circuits
Protection
name
Complete
shutdown
Restart
directly
Restart
after
100
ms
PROT pin
active
DIAG1 pin
active
DIAG2 pin
active
TFB
[1]
N N N N Y
[2]
N
OTP Y N Y N N Y
OCP Y
[3]
N
[3]
Y
[3]
Y N Y
WP N
[4]
Y N N N Y
UVP Y N Y N N Y
OVP Y N Y N N Y
UBP Y N Y N N Y
CP Y N Y
[5]
N N Y
