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TDA8954J/N1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 7 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
The smooth transition between Mute and Operating modes causes a gradual increase in
the DC offset output voltage, which becomes inaudible (no pop noise because the DC
offset voltage rises smoothly). An overview of the start-up timing is provided in
Figure 5.
For proper switch-off, the MODE pin should be forced LOW at least 100 ms before the
supply lines (V
DD
and V
SS
) drop below 12.5 V.
(1) First
1
⁄
4
pulse down.
Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms
before the output starts switching. The audio signal will become available once V
MODE
reaches the
Operating mode level (see
Table 9), but not earlier than 150 ms after switching to Mute. To start-up
pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms
for the transition between Mute and Operating modes.
Lower diagram: When switching directly from Standby to Operating mode, there is a delay of
100
ms before the outputs start switching. The audio signal becomes available after a second
delay of 50
ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin
MODE be at least 500
ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
2.2 V < V
MODE
< 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND)
time
001aah65
7
V
MODE
100 ms
50 ms
modulated PWM
> 350 ms
2.2 V < V
MODE
< 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND)
time
V
MODE
100 ms
50 ms
modulated PWM
> 350 ms
(1)
(1)
TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 8 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
8.2 Diagnostics
The TDA8954 provides two diagnostic signals on pins DIAG1 and DIAG2. Both are
open-drain outputs that can be pulled up via a resistor (10 kΩ recommended) to a
maximum of 5
V relative to the GND pin. The maximum input current on these pins is
1
mA.
Pin DIAG1 provides a TFB warning signal. Pin DIAG2 can be used to monitor the OCP
status and the protection status (whether one of the protection circuits has switched off the
amplifier).
Details of the timing of these signals can be found in Section 8.4.1.1 and Section 8.4.2;
see also Table 5.
8.3 Pulse-width modulation frequency
The amplifier output signal is a PWM signal with a typical carrier frequency of between
250
kHz and 450 kHz. A second-order LC demodulation filter on the output converts the
PWM signal into an analog audio signal. The carrier frequency, f
OSC
, is determined by an
external resistor, R
OSC
, connected between pins OSC and OSCREF. The optimal carrier
frequency setting is between 250
kHz and 450 kHz.
The carrier frequency is set to 335 kHz by connecting an external 30 kΩ resistor between
pins OSC and OSCREF (see
Figure 6).
If two or more Class D amplifiers are used in the same audio application, an external clock
circuit must be used to synchronize all amplifiers (see
Section 14.4). This will ensure that
they operate at the same switching frequency, thus avoiding beat tones (if the switching
frequencies are different, audible interference known as ‘beat tones’ can be generated).
Fig 6. Carrier frequency as a function of R
OSC
R
OSC
(kΩ)
20 454030 3525
010aaa596
300
400
500
f
OSC
(kHz)
200
TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 9 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
8.4 Protection
The following protection circuits are incorporated into the TDA8954:
• Thermal protection:
– Thermal FoldBack (TFB)
– OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protection:
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• Clock Protection (CP)
How the device reacts to a fault condition depends on which protection circuit has been
activated.
8.4.1 Thermal protection
The TDA8954 employes an advanced thermal protection strategy. A TFB function
gradually reduces the output power within a defined temperature range. If the temperature
continues to rise, OTP is activated to shut the device down completely.
8.4.1.1 Thermal FoldBack (TFB)
If the junction temperature (T
j
) exceeds the thermal foldback activation threshold
(T
act(th_fold)
), the gain is gradually reduced. This reduces the output signal amplitude and
the power dissipation, eventually stabilizing the temperature.
When T
j
reaches T
act(warn)th_fold
, the TFB warning signal is activated (pin DIAG1 goes
LOW). Thermal foldback is activated if the temperature rises to T
act(th_fold)
(see Figure 7).
The TFB warning signal is reset when the temperature drops below T
rst(warn)th_fold
again
(see
Figure 8).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

TDA8954J/N1,112

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Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers 2-CH 210 W class-D power amplifier
Lifecycle:
New from this manufacturer.
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