TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 19 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
[1] V
DD
is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] V
SS
is the supply voltage on pins VSSP1, VSSP2 and VSSA.
[3] Unbalance protection activated when V
DDA
> 2 × |V
SSA
| OR |V
SSA
| > 2 × V
DDA
.
[4] With respect to SGND (0 V).
[5] The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is
determined by the time-constant of the RC network on pin MODE; see
Figure 11.
I
DD(tot)
total positive supply current the sum of the currents through pins
VDDA, VDDP1 and VDDP2
Operating mode; no load; no filter;
no RC-snubber network connected;
- 50 60 mA
I
SS(tot)
total negative supply current the sum of the currents through pins
VSSA, VSSP1 and VSSP2
Operating mode; no load; no filter;
no RC-snubber network connected;
- 65 75 mA
I
stb
standby current - 490 650 μA
Mode select input; pin MODE
V
MODE
voltage on pin MODE referenced to SGND
[4]
0 - 8 V
Standby mode
[4][5]
0 - 0.8 V
Mute mode
[4][5]
2.2 - 3.0 V
Operating mode
[4][5]
4.2 - 5.5 V
Operating mode without TFB
[4][5]
6.6 - 8
I
I
input current V
I
= 5.5 V - 110 150 μA
Audio inputs; pins IN1M, IN1P, IN2P and IN2M
V
I
input voltage DC input
[4]
- 0 - V
Amplifier outputs; pins OUT1 and OUT2
V
O(offset)
output offset voltage SE; Mute mode 37 - +37 mV
SE; Operating mode
[6]
150 - +150 mV
BTL; Mute mode 30 - +30 mV
BTL; Operating mode
[6]
210 - +210 mV
Stabilizer output; pin STABI
V
O(STABI)
output voltage on pin STABI Mute and Operating modes; with
respect to VSSA
9.5 10 10.5 V
Temperature protection
T
rst(warn)th_fold
thermal foldback warning
reset
temperature
- 138 - °C
T
act(warn)th_fold
thermal foldback warning
activation temperature
- 139 - °C
T
act(th_fold)
thermal foldback activation
temperature
V
MODE
< 5.5 V - 145 - °C
T
hg(th_fold)
thermal foldback half gain
temperature
V
MODE
< 5.5 V; gain = 24 dB - 153 - °C
T
act(th_prot)
thermal protection activation
temperature
- 154 - °C
Table 9. Static characteristics …continued
V
DD
= 41 V; V
SS
=
41 V; f
osc
= 335 kHz; T
amb
= 25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 20 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
[6] DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused
by any DC output offset is determined by the time-constant of the RC network on pin MODE.
13. Dynamic characteristics
13.1 Switching characteristics
[1] When using an external oscillator, the frequency f
track
(500 kHz minimum, 1000 kHz maximum) will result in a PWM frequency f
osc
(250
kHz minimum, 500 kHz maximum) due to the internal clock divider; see Section 8.3.
[2] When t
r(i)
> 100 ns, the output noise floor will increase.
Fig 11. Behavior of mode selection pin MODE
010aaa56
4
0 0.8
V
O
[V]
V
MODE
[V]
V
O(offset)(on)
V
O(offset)(mute)
2.2 4.2 5.5 6.6 83.0
Slope is directly related to the time constant
of the RC network on the MODE pin
On
On
no TFB
Mute
Standby
Table 10. Dynamic characteristics
V
DD
= 41 V; V
SS
=
41 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Internal oscillator
f
osc(typ)
typical oscillator frequency R
OSC
= 30.0 kΩ 290 335 365 kHz
f
osc
oscillator frequency 250 - 450 kHz
External oscillator input or frequency tracking; pin OSC
V
OSC
voltage on pin OSC HIGH-level SGND + 4.5 SGND + 5 SGND + 6 V
V
trip
trip voltage - SGND + 2.5 - V
f
track
tracking frequency
[1]
500 - 1000 kHz
Z
i
input impedance 1 - - MΩ
C
i
input capacitance - - 15 pF
t
r(i)
input rise time from SGND + 0 V to
SGND + 5 V
[2]
- - 100 ns
TDA8954_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 24 December 2009 21 of 46
NXP Semiconductors
TDA8954
2 × 210 W class-D power amplifier
13.2 Stereo SE configuration characteristics
[1] R
sL
is the series resistance of the low-pass LC filter inductor used in the application.
[2] Output power is measured indirectly; based on R
DSon
measurement; see Section 14.3.
[3] One channel driven at maximum output power; the other channel driven at one eight maximum output power.
[4] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter.
[5] V
ripple
= V
ripple(max)
= 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[7] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[8] P
o
= 1 W; f
i
= 1 kHz.
[9] V
i
= V
i(max)
= 1 V (RMS); f
i
= 1 kHz.
[10] Leads and bond wires included.
Table 11. Dynamic characteristics
V
DD
= 41 V; V
SS
=
41 V; R
L
= 4
Ω
; f
i
= 1 kHz; f
osc
= 335 kHz; R
sL
< 0.1
Ω
[1]
; T
amb
= 25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
P
o
output power L = 15 μH; C
LC
= 680 nF; T
j
= 85 °C
[2]
THD = 0.5 %; R
L
= 4 Ω - 160 - W
THD = 10 %; R
L
= 4 Ω - 210 - W
THD = 10 %; R
L
= 3 Ω; V
P
= ±39 V
[3]
- 235 - W
THD total harmonic distortion P
o
= 1 W; f
i
= 1 kHz
[4]
- 0.03 0.1 %
P
o
= 1 W; f
i
= 6 kHz
[4]
- 0.05 - %
G
v(cl)
closed-loop voltage gain 29 30 31 dB
SVRR supply voltage ripple rejection between pins VDDPn and SGND
Operating mode; f
i
= 100 Hz
[5]
- 90 - dB
Operating mode; f
i
= 1 kHz
[5]
- 70 - dB
Mute mode; f
i
= 100 Hz
[5]
- 75 - dB
Standby mode; f
i
= 100 Hz
[5]
- 120 - dB
between pins VSSPn and SGND
Operating mode; f
i
= 100 Hz
[5]
- 80 - dB
Operating mode; f
i
= 1 kHz
[5]
- 60 - dB
Mute mode; f
i
= 100 Hz
[5]
- 80 - dB
Standby mode; f
i
= 100 Hz
[5]
- 115 - dB
Z
i
input impedance between an input pin and SGND 45 56 - kΩ
V
n(o)
output noise voltage Operating mode; inputs shorted
[6]
- 160 - μV
Mute mode
[7]
- 85 - μV
α
cs
channel separation
[8]
- 70 - dB
G
v
| voltage gain difference - - 1 dB
α
mute
mute attenuation f
i
= 1 kHz; V
i
= 2 V (RMS)
[9]
- 75 - dB
CMRR common mode rejection ratio V
i(CM)
= 1 V (RMS) - 75 - dB
η
po
output power efficiency SE, R
L
= 4 Ω - 93 - %
SE, R
L
= 3 Ω - 90 - %
BTL, R
L
= 8 Ω - 93 - %
R
DSon(hs)
high-side drain-source on-state resistance
[10]
- 110 - mΩ
R
DSon(ls)
low-side drain-source on-state resistance
[10]
- 105 - mΩ

TDA8954J/N1,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers 2-CH 210 W class-D power amplifier
Lifecycle:
New from this manufacturer.
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