AD7706BRZ Datasheet AD7705BRUZ, AD7705BNZ, AD7705BRZ-REEL | P34-P36

AD7705/AD7706

Rev. C | Page 34 of 44

MICROCOMPUTER/MICROPROCESSOR

INTERFACING

The flexible serial interface of the AD7705/AD7706 allows easy

interfacing to most microcomputers and microprocessors.

The flowchart in

Figure 21 outlines the sequence to follow

when interfacing a microcontroller or microprocessor to the

AD7705/AD7706.

Figure 22 through Figure 24 show typical

interface circuits.

The serial interface is capable of operating from three wires and

is compatible with SPI interface protocols. The 3-wire operation

makes these parts ideal for an isolated system in which minimizing

the number of interface lines minimizes the number of

opto-isolators required in the system. The serial clock input is a

Schmitt-triggered input to accommodate slow edges from opto-

couplers. The rise and fall times of other digital inputs to the

AD7705/AD7706 should be no longer than 1 μs.

Most of the registers on the AD7705/AD7706 are 8-bit registers,

which facilitates easy interfacing to the 8-bit serial ports of micro-

controllers. The data register on the AD7705/AD7706 is 16 bits,

and the offset and gain registers are 24-bit registers, but data

transfers to these registers can consist of multiple 8-bit transfers

to the serial port of the microcontroller. DSP processors and

microprocessors generally transfer 16 bits of data in a serial data

operation. Some of these processors, such as the ADSP-2105,

have the facility to program the number of cycles in a serial

transfer. This allows the user to tailor the number of bits in any

transfer to match the length of the required register in the

AD7705/AD7706.

Because some registers on the AD7705/AD7706 are only 8 bits

long, successive write operations to two of these registers can be

handled as a single 16-bit data transfer. For example, to update

the setup register, the processor must write to the communication

done in a single 16-bit transfer, because once the eight serial

clocks of the write operation to the communication register are

complete, the part immediately sets up for a write operation to

the setup register.

AD7705/AD7706-to-68HC11 Interface

Figure 22 shows an interface between the AD7705/AD7706 and

the 68HC11 microcontroller. The diagram shows the minimum

(3-wire) interface with

on the AD7705/AD7706 hardwired

low. In this scheme, the

DRDY

bit of the communication register

is monitored to determine when the data register is updated. An

alternative scheme, which increases the number of interface lines

to four, is to monitor the

DRDY

output line from the AD7705/

AD7706. Monitoring the

DRDY

line can be done in two ways.

First,

DRDY

can be connected to a 68HC11 port bit (such as

PC0) that is configured as an input. This port bit is then polled

to determine the status of

DRDY

The second scheme is to use an interrupt-driven system, in

which case the

DRDY

output is connected to the

IRQ

input of

the 68HC11. For interfaces that require control of the

input

on the AD7705/AD7706, a port bit of the 68HC11 (such as

PC1) that is configured as an output can be used to drive the

input.

SCK

MISO

MOSI

68HC11

RESET

SCLK

DOUT

DIN

AD7705/AD7706

01166-022

Figure 22. AD7705/AD7706-to-68HC11 Interface

The 68HC11 is configured in master mode with its CPOL and

CPHA bits set to Logic 1. When the 68HC11 is configured like

this, its SCLK line idles high between data transfers. The AD7705/

AD7706 are not capable of a full duplex operation. If the AD7705/

AD7706 are configured for a write operation, no data appears

on the DOUT lines, even when the SCLK input is active.

Similarly, if the AD7705/AD7706 are configured for a read

operation, data presented to the part on the DIN line is ignored,

even when SCLK is active.

Coding for an interface between the 68HC11 and the AD7705/

AD7706 is given in the

C Code for Interfacing AD7705 to

68HC11 section. In this example, the

DRDY

output line of the

AD7705 is connected to the PC0 port bit of the 68HC11 and is

polled to determine its status.

P3.0

P3.1

8XC51

RESET

SCLK

DOUT

DIN

AD7705/AD7706

01166-023

Figure 23. AD7705/AD7706-to-8XC51 Interface

AD7705/AD7706

Rev. C | Page 35 of 44

AD7705/AD7706-to-8051 Interface

An interface circuit between the AD7705/AD7706 and the 8XC51

microcontroller is shown in

Figure 23. The diagram shows the

minimum number of interface connections with

on the

AD7705/AD7706 hardwired low. In the case of the 8XC51

interface, the minimum number of interconnects is two. In this

scheme, the

DRDY

bit of the communication register is monitored

to determine when the data register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the

DRDY

output line from the AD7705/AD7706.

Monitoring the

DRDY

line can be done in two ways. First,

DRDY

can be connected to a 8XC51 port bit (such as P1.0) that is

configured as an input. This port bit is then polled to determine

the status of

DRDY

. The second scheme is to use an interrupt-

driven system, in which case the

DRDY

output is connected to

the

INT1

input of the 8XC51. For interfaces that require control

of the

input on the AD7705/AD7706, a port bit of the 8XC51

(such as P1.1) that is configured as an output can be used to

drive the

input. The 8XC51 is configured in Mode 0 serial

interface mode. Its serial interface contains a single data line.

As a result, the DOUT and DIN pins of the AD7705/

AD7706 should be connected together with a 10 kΩ pull-up

resistor. The serial clock on the 8XC51 idles high between data

transfers. During a write operation, the 8XC51 outputs the LSB

first. Because the AD7705/AD7706 expect the MSB first, the

data must be rearranged before being written to the output

serial register. Similarly, during a read operation, the AD7705/

AD7706 output the MSB first, and the 8XC51 expects the LSB

first. Therefore, the data read into the serial buffer must be

rearranged before the correct data-word from the AD7705/

AD7706 is available in the accumulator.

RFS

ADSP-2103/

ADSP-2105

RESET

SCLK

DOUT

DIN

AD7705/AD7706

TFS

SCLK

01166-024

Figure 24. AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface

AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface

Figure 24 shows an interface between the AD7705/AD7706 and

the ADSP-2103/ADSP-2105 DSP processor. In the interface

shown, the

DRDY

bit of the communication register is monitored

to determine when the data register is updated. The alternative

scheme is to use an interrupt-driven system, in which case the

DRDY

output is connected to the

IRQ2

input of the ADSP-2103/

ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105

is set up for alternate framing mode. The

RFS

and

TFS

pins of

the ADSP-2103/ADSP-2105 are configured as active low outputs,

and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is

configured as an output. The

for the AD7705/AD7706 is

active when either the

RFS

TFS

outputs from the ADSP-2103/

ADSP-2105 are active. The serial clock rate on the ADSP-2103/

ADSP-2105 should be limited to 3 MHz to ensure correct

operation with the AD7705/AD7706.

CODE FOR SETTING UP THE AD7705/AD7706

The following section shows a set of read and write routines in

C code for interfacing the 68HC11 microcontroller to the AD7705.

The sample program sets up the various registers on the AD7705

and reads 1000 samples from one channel into the 68HC11. The

setup conditions on the part are the same as those outlined for the

flowchart of

Figure 21. In the example code given here, the

DRDY

output is polled to determine if a new valid word is available in

the data register. The same sequence is applicable for the AD7706.

The sequence of events in this program are as follows:

Write to the communication register, selecting Channel 1

as the active channel and setting the next operation to be a

write to the clock register.

Write to the clock register, setting the CLKDIV bit, which

divides the external clock internally by two. This assumes

that the external crystal is 4.9512 MHz. The update rate is

selected to be 50 Hz.

Write to the communication register selecting Channel 1 as

the active channel and setting the next operation to be a

write to the setup register.

Write to the setup register, setting the gain to 1, setting

bipolar mode, buffer off, clearing the filter

synchronization, and initiating a self-calibration.

Poll the

DRDY

output.

Read the data from the data register.

Repeat Steps 5 and 6 (loop) until the specified number of

samples has been taken from the selected channel.

AD7705/AD7706

Rev. C | Page 36 of 44

C Code for Interfacing AD7705 to 68HC11

#include <math.h>

#include <io6811.h>

#define NUM_SAMPLES 1000 /* change the number of data samples */

#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */

Writetoreg (int);

Read (int,char);

char *datapointer = store;

char store[NUM_SAMPLES*MAX_REG_LENGTH + 30];

void main()

{

/* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is

made as

an output */

char a;

DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */

PORTC | = 0x04; /* make the /CS line high */

Writetoreg(0x20); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the clock register */

Writetoreg(0x0C); /* master clock enabled, 4.9512MHz Clock, set output rate to 50Hz*/

Writetoreg(0x10); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the setup register */

Writetoreg(0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/

while(PORTC & 0x10); /* wait for /DRDY to go low */

for(a=0;a<NUM_SAMPLES;a++);

{

Writetoreg(0x38); /*set the next operation for 16 bit read from the data register */

Read(NUM_SAMPES,2);

}

Writetoreg(int byteword);

{

int q;

SPCR = 0x3f;

SPCR = 0X7f; /* this sets the WiredOR mode(DWOM=1), Master mode(MSTR=1), SCK idles high(CPOL=1), /SS can be low

always (CPHA=1), lowest clock speed(slowest speed which is master clock /32 */

DDRD = 0x18; /* SCK, MOSI outputs */

q = SPSR;

q = SPDR; /* the read of the status register and of the data register is needed to clear the interrupt which tells

the user that the

data transfer is complete */

PORTC &= 0xfb; /* /CS is low */

SPDR = byteword; /* put the byte into data register */

while(!(SPSR & 0x80)); /* wait for /DRDY to go low */

PORTC |= 0x4; /* /CS high */

}

Read(int amount, int reglength)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

AD7706BRZ

Mfr. #:

Buy AD7706BRZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3V/5V 1mW 3-Ch Pseudo Diff 16-Bit

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AD7706BRZ

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