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AD7706BRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
AD7705/AD7706
Rev. C | Page 4 of 44
PRODUCT HIGHLIGHTS
1. The AD7705/AD7706 devices consume less than 1 mW at
3 V supplies and 1 MHz master clock, making them ideal
for use in low power systems. Standby current is less than 8
μA.
2. The programmable gain input allows the AD7705/AD7706
to accept input signals directly from a strain gage or
transducer, removing a considerable amount of signal
conditioning.
3. The AD7705/AD7706 are ideal for microcontroller or DSP
processor applications with a 3-wire serial interface,
reducing the number of interconnect lines and reducing
the number of opto-couplers required in isolated systems.
4. The parts feature excellent static performance
specifications with 16 bits, no missing codes, ±0.003%
accuracy, and low rms noise (<600 nV). Endpoint errors
and the effects of temperature drift are eliminated by on-
chip calibration options, which remove zero-scale and full-
scale errors.
AD7705/AD7706
Rev. C | Page 5 of 44
SPECIFICATIONS
V
DD
= 3 V or 5 V, REF IN(+) = 1.225 V with V
DD
= 3 V, and 2.5 V with V
DD
= 5 V; REF IN(−) = GND; MCLK IN = 2.4576 MHz, unless
otherwise noted. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 16 Bits min Guaranteed by design, filter notch < 60 Hz
Output Noise
See
Table 5 and
Table 7
Depends on filter cutoffs and selected gain
Integral Nonlinearity
2
±0.003 % of FSR max Filter notch < 60 Hz, typically ±0.0003%
Unipolar Offset Error
3
Unipolar Offset Drift
4
0.5 μV/°C typ
Bipolar Zero Error
3
Bipolar Zero Drift
4
0.5 μV/°C typ For gains 1, 2, and 4
0.1 μV/°C typ For gains 8, 16, 32, 64, and 128
Positive Full-Scale Error
3, 5
Full-Scale Drift
4, 6
0.5 μV/°C typ
Gain Error
3, 7
Gain Drift
4, 8
0.5
ppm of FSR/°C
typ
Bipolar Negative Full-Scale Error
2
±0.003 % of FSR typ Typically ±0.001%
Bipolar Negative Full-Scale Drift
4
1 μV/°C typ For gains of 1 to 4
0.6 μV/°C typ For gains of 8 to 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN, unless otherwise
noted
Common-Mode Rejection (CMR)
2
V
DD
= 5 V
Gain = 1 96 dB typ
Gain = 2 105 dB typ
Gain = 4 110 dB typ
Gain = 8 to 128 130 dB typ
V
DD
= 3 V
Gain = 1 105 dB typ
Gain = 2 110 dB typ
Gain = 4 120 dB typ
Gain = 8 to 128 130 dB typ
Normal-Mode 50 Hz Rejection
2
98 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
2
98 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
2
150 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
2
150 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f
NOTCH
Absolute/Common-Mode REF IN
Voltage
2
GND to V
DD
V min to V max
Absolute/Common-Mode AIN
Voltage
2, 9, 10
GND − 100 mV V min BUF bit of setup register = 0
V
DD
+ 30 mV V max
Absolute/Common-Mode AIN
Voltage
2, 9
GND + 50 mV V min BUF bit of setup register = 1
V
DD
− 1.5 V V max
AIN DC Input Current
2
1 nA max
AIN Sampling Capacitance
2
10 pF max
AIN Differential Voltage Range
11
0 to +V
REF
/gain
12
nom
Unipolar input range (B
/U bit of setup register = 1)
±V
REF
/gain nom
Bipolar input range (B
/U bit of setup register = 0)
AD7705/AD7706
Rev. C | Page 6 of 44
Parameter B Version
1
Unit Conditions/Comments
AIN Input Sampling Rate, f
S
Gain × f
CLKIN
/64 For gains of 1 to 4
f
CLKIN
/8 For gains of 8 to 128
Reference Input Range
REF IN(+) − REF IN(−) Voltage 1/1.75 V min/V max
V
DD
= 2.7 V to 3.3 V
V
REF
= 1.225 ± 1% for specified performance
REF IN(+) − REF IN(−) Voltage 1/3.5 V min/V max
V
DD
= 4.75 V to 5.25 V
V
REF
= 2.5 ± 1% for specified performance
REF IN Input Sampling Rate, f
S
f
CLKIN
/64
LOGIC INPUTS
Input Current
All Inputs, Except MCLK IN ±1 μA max Typically ±20 nA
MCLK IN ±10 μA max Typically ±2 μA
All Inputs, Except SCLK and MCLK IN
Input Low Voltage, V
INL
0.8 V max V
DD
= 5 V
0.4 V max V
DD
= 3 V
Input High Voltage, V
INH
2.0 V min V
DD
= 3 V and 5 V
SCLK Only (Schmitt-Triggered Input) V
DD
= 5 V nominal
V
T+
1.4/3 V min/V max
V
T−
0.8/1.4 V min/V max
V
T+
− V
T−
0.4/0.8 V min/V max
SCLK Only (Schmitt-Triggered Input) V
DD
= 3 V nominal
V
T+
1/2 V min/V max
V
T−
0.4/1.1 V min/V max
V
T+
− V
T−
0.375/0.8 V min/V max
MCLK IN Only V
DD
= 5 V nominal
Input Low Voltage, V
INL
0.8 V max
Input High Voltage, V
INH
3.5 V min
MCLK IN Only V
DD
= 3 V nominal
Input Low Voltage, V
INL
0.4 V max
Input High Voltage, V
INH
2.5 V min
LOGIC OUTPUTS (Including MCLK OUT)
Output Low Voltage, V
OL
0.4 V max I
SINK
= 800 μA, except for MCLK OUT;
13
V
DD
= 5 V
Output Low Voltage, V
OL
0.4 V max I
SINK
= 100 μA, except for MCLK OUT;
13
V
DD
= 3 V
Output High Voltage, V
OH
4 V min I
SOURCE
= 200 μA, except for MCLK OUT;
13
V
DD
= 5 V
Output High Voltage, V
OH
V
DD
− 0.6 V min I
SOURCE
= 100 μA, except for MCLK OUT;
13
V
DD
= 3 V
Floating State Leakage Current ±10 μA max
Floating State Output Capacitance
14
9 pF typ
Data Output Coding Binary Unipolar mode
Offset binary Bipolar mode
SYSTEM CALIBRATION
Positive Full-Scale Limit
15
(1.05 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
Negative Full-Scale Limit
15
−(1.05 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
Offset Limit
15
−(1.05 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
Input Span
16
(0.8 × V
REF
)/gain V min Gain is the selected PGA gain (1 to 128)
(2.1 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

AD7706BRZ

Mfr. #:
Buy AD7706BRZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V 1mW 3-Ch Pseudo Diff 16-Bit
Lifecycle:
New from this manufacturer.
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