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TDA8007BHL/C4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 13 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.1 General registers
8.2.1.1 Card select register
The Card Select Register (CSR) is used for selecting the card on which the UART will act,
and also to reset the ISO UART.
[1] Register value at reset: all significant bits are cleared after reset, except bits CS7 to CS4 which are set to
their default value
[1] Bits SC1, SC2 and SC3 must be set at one at a time. After reset no card is selected by default
8.2.1.2 Hardware status register
The Hardware Status Register (HSR) gives the status of the chip after a hardware
problem has been detected.
[1] Register value at reset: all significant bits are cleared after reset, except bit SUPL which is set within
pulse RSTOUT.
Table 4. Register CSR (address 00h; write and read)
[1]
7 6 5 4 3 2 1 0
CS7 CS6 CS5 CS4 RIU
SC3 SC2 SC1
Table 5. Register CSR (address 00h; write and read)
[1]
Bit Symbol Description
7CS7 IC identifier: default value for identification the IC
0010 = TDA8007BHL/C2
0011 = TDA8007BHL/C3 or TDA8007BHL/C4
6CS6
5CS5
4CS4
3RIU
reset ISO UART: When reset, this bit resets a large part of the UART
registers to their initial value. Bit RIU must be reset before any
activation; logic 0 for at least 10 ns duration. Bit RIU must be set to
logic 1 by software before any action on the UART can take place.
2SC3 select card 3: If bit SC3 = 1, then card 3 is selected.
1SC2 select card 2: If bit SC2 = 1, then card 2 is selected.
0SC1 select card 1: If bit SC1 = 1, then card 1 is selected.
Table 6. Register HSR (address 0Fh; read only)
[1]
7 6 5 4 3 2 1 0
HS7 PRTL2 PRTL1 SUPL PRL2 PRL1 INTAUXL PTL
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 14 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
When at least one of the bits PRTL2, PRTL1, PRL2, PRL1 or PTL is high, then INT is low.
The bits having caused the interrupt are cleared when register HSR has been read-out.
The same occurs with INTAUXL, if not disabled.
In case of an emergency deactivation (by bits PRTL2, PRTL1, SUPL, PRL2, PRL1
or PTL), bit START (bit 0 in the PCR) is automatically reset by hardware.
At power-on, or after a supply voltage drop-out, bit SUPL is set and pin INT
= low. Pin INT
will return to high level at the end of the alarm pulse RSTOUT (see Figure 3
).
Bit SUPL will be reset only after a status register read-out outside the alarm pulse.
A minimum time of 2 µs is needed between two successive read operations of
register HSR, as well as between reading of register HSR and activation (write in
register PCR).
8.2.1.3 Time-out registers
The three Time-Out Registers (TOR1, TOR2 and TOR3) form a programmable 24-bit ETU
counter, or two independent counters (one 16-bit and one 8-bit). The value to load in
registers TOR1, TOR2 and TOR3 is the number of ETU to count. The time-out counters
may only be used when a card is active with a running clock.
[1] Register value at reset: all bits are cleared after reset.
[1] Register value at reset: all bits are cleared after reset.
Table 7. Description of HSR bits
Bit Symbol Description
7 HS7 not used
6PRTL2protection 2: Bit PRTL2 = 1 when a fault has been detected on card
reader 2. Bit PRTL 2 is the OR-function of the protection on pin V
CC2
and pin RST2.
5PRTL1protection 1:. Bit PRTL1 = 1 when a fault has been detected on card
reader 1. Bit PRTL 1 is the OR-function of the protection on pin V
CC1
and pin RST1.
4SUPLsupervisor latch. Bit SUPL = 1 when the supervisor has been
activated.
3PRL2 presence latch 2: Bit PRL2 = 1 when a level change has occurred on
pin PRES2.
2PRL1 presence latch 1: Bit PRL1 = 1 when a level change has occurred on
pin PRES1.
1 INTAUXL auxiliary interrupt change: Bit INTAUXL = 1 if the level on
pin INTAUX has been changed.
0PTL overheating: Bit PTL = 1 if overheating has occurred.
Table 8. Register TOR1 (address 09H; write only)
[1]
7 6 5 4 3 2 1 0
TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0
Table 9. Register TOR2 (address 0AH; write only)
[1]
7 6 5 4 3 2 1 0
TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 15 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
[1] Register value at reset: all bits are cleared after reset.
8.2.1.4 Time-out configuration register
The Time-Out Configuration (TOC) register is used for setting different configurations of
the time-out counter as given in Table 11; all other configurations are undefined.
[1] Register value at reset: all bits are cleared after reset.
Table 10. Register TOR3 (address 0Bh; write only)
[1]
7 6 5 4 3 2 1 0
TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16
Table 11. Register TOC (address 0Bh; read and write)
[1]
7 6 5 4 3 2 1 0
TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0
Table 12. Card registers (address 00h to F5h
Register Description
00H All counters are stopped.
05H Counters 2 and 3 are stopped; counter 1 continues to operate in auto-reload mode.
61H Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value
stored in registers TOR3 and TOR2 is started after 61H is written in register TOC. An
interrupt is given, and bit TO3 is set within register USR when the terminal count is
reached. The counter is stopped by writing 00H in register TOC, and should be
stopped before reloading new values in registers TOR2 and TOR3.
65H Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.
Counter 1 starts counting the content of register TOR1 on the first START bit
(reception or transmission) detected on pin I/O after 65H is written in register TOC.
When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
register USR is set, and the counter automatically restarts the same count until it is
stopped. It is not allowed to change the content of register TOR1 during a count.
Counters 3 and 2 are wired as a single 16-bit counter and start counting the value in
registers TOR3 and TOR2 when 65H is written in register TOC. When the counter
reaches its terminal count, an interrupt is given and bit TO3 is set within register USR.
Both counters are stopped when 00H is written in register TOC. Counters 3 and 2
shall be stopped by writing 05H in register TOC before reloading new values in
registers TOR2 and TOR3.
68H Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in
registers TOR3, TOR2 and TOR1 is started after 68H is written in register TOC. The
counter is stopped by writing 00H in register TOC. It is not allowed to change the
content of registers TOR3, TOR2 and TOR1 within a count.
71H Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value
stored in registers TOR3 and TOR2 and is started on the first START bit detected on
pin I/O (reception or transmission) after the value has been written, and then on each
subsequent START bit. It is possible to change the content of registers TOR3 and
TOR2 during a count; the current count will not be affected and the new count value
will be taken into account at the next START bit. The counter is stopped by writing
00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1 must not
be all zero.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

TDA8007BHL/C4,118

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Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC 12bit 2-I/Os 5V
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