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TDA8007BHL/C4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 25 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
4PDWNpower-down mode. If bit PDWN is set by software, the crystal
oscillator is stopped. This mode allows low power consumption in
applications where this is required. During the Power-down mode, it is
not possible to select a card other than the one currently selected.
There are five ways of escaping from the Power-down mode:
- withdraw card 1 or 2
- Select the TDA8007BHL/C4 by resetting bit CS (this assumes that
the TDA8007BHL/C4 had been deselected after setting Power-down
mode)
- insert card 1 or card 2
- Bit INTAUXL has been set due to a change on pin INTAUX
- If pin CS = low permanently, reset bit PDWN by software.
After any of these events, the TDA8007BHL/C4 will leave the
Power-down mode.
Except in the case of a read operation of register HSR, signal INT
will
be pulled to low level. The system microcontroller may then read the
status registers after 5 ms, and signal INT
will return to high level (if the
system microcontroller has woken the TDA8007BHL/C4 by re-selecting
it, then no bits will be set in the status registers).
Note that the Power-down mode can only be entered if bit SUPL has
been cleared.
3 SAN synchronous/asynchronous card. Bit SAN = 1 by software if a
synchronous card is expected. The UART is then bypassed and only
bit 0 in registers URR and UTR is connected to pin I/O. In this case the
clock is controlled by bit SC in register CCR.
2 AUTOCONV auto convention. If bit AUTOCONV = 1, then the convention is set by
software using bit CONV in register UCR1. If the bit is reset, then the
configuration is automatically detected on the first received character
whilst the start session (bit SS) is set.
Bit AUTOCONV must not be changed during a card session.
1CKU clock UART. For baud rates other than those given in Table 24, there is
the possibility to set bit CKU = 1. In this case, the ETU will last half the
number of card clock cycles equal to prescaler PDRx. Note that
bit CKU = 1 has no effect if f
CLK
= f
XTAL
. This means, for example, that
76800 baud is not possible when the card is clocked with the external
frequency on pin XTAL1.
0 PSC prescale Select. If bit PSC = 1, then the prescaler value is 32. If
bit PSC = 0, then the prescaler value is 31. One ETU will last a number
of cards clock cycles equal to prescaler PDRx. All baud rates specified
in the ISO 7816 norm are achievable with this configuration (see
Table 24 ).
Table 23. Description of UCR2 bits
Bit Symbol Description
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 26 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
[1] Example: 31;12 in the table means prescaler set to 31 and PDR set to 12
8.2.3.3 Guard Time Registers (GTR)
The guard time registers GTR1, GTR2 and GTR3 are used for storing the number of
guard ETU given by the card during ATR. In transmission mode, the UART will wait this
number of ETU before transmitting the character stored in register UTR.
When register GTRx = FF:
• In protocol T = 1
TDA8007BHL/C4 operates at 10.8 ETU
• In protocol T = 0
TDA8007BHL/C4 operates at 11.8 ETU.
[1] Register value at reset: all bits are cleared after reset.
8.2.3.4 UART Configuration Registers (UCR) 1
The UART configuration registers 1 (UCR11, UCR21 and UCR31) set the parameters of
the ISO UART.
[1] Register value at reset: all bits are cleared after reset.
Table 24. Baud rate selection using values F and D
[1]
PSC = 31: f
CLK
= 3.58 MHz; PSC = 32: f
CLK
= 4.92 MHz
D F
0 1 2 3 4 5 6 9 10 11 12 13
1 31;12
9600
31;12
9600
31;18
6400
31;24
4800
31;36
3200
31;48
2400
31;60
1920
32;16
9600
32;24
6400
32;32
4800
32;48
3200
32;64
2400
2 31;6
19200
31;6
19200
31;9
12800
31;12
9600
31;18
6400
31;24
4800
31;30
3840
32;8
19200
32;12
12800
32;16
9600
32;24
6400
32;32
4800
3 31;3
38400
31;3
38400
31;6
19200
31;9
12800
31;12
9600
31;15
7680
32;4
38400
32;6
25600
32;8
19200
32;12
12800
32;16
9600
4 31;3
38400
31;6
19200
32;2
76800
32;3
51300
32;4
38400
32;6
25600
32;8
19200
5 31;3
38400
32;1
153600
32;2
76800
32;3
51300
32;4
38400
6 32;1
153600
32;2
76800
8 31;1
115200
31;1
11
5200
31;2
57600
31;3
38400
31;4
28800
31;5
23040
32;2
76800
32;4
38400
931;3
38400
Table 25. Register GTR1, GTR2, GTR3 (address 05H; read and write)
[1]
7 6 5 4 3 2 1 0
GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0
Table 26. Register UCR11, UCR21 and UCR31 (address 06H; read and write)
[1]
7 6 5 4 3 2 1 0
UC17 FIP FC PROT T/R LCT SS CONV
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 27 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.3.5 Clock Configuration Registers (CCR)
The clock configuration registers CCR1, CCR2 and CCR3 relate the clock signals:
• For cards 1 and 2, register CCRx defines the clock for the selected card
• For cards 1, 2 and 3, register CCRx defines the clock to the ISO UART. It should be
noted that, if bit CKU in the prescaler register of the selected card (register UCR2) is
set, then the ISO UART is clocked at twice the frequency of the card, which allows
baud rates not foreseen in ISO 7816 norm to be reached.
[1] Register value at reset: all bits are cleared after reset.
Table 27. Description of UCRx1 bits
Bit Symbol Description
7 UC17 not used
6FIP Force Inverse Parity (FIP). If bit FIP is set to logic 1, the UART will
NAK a correctly received character, and will transmit characters with
wrong parity bits.
5FC Test. Bit FC is a test bit, and must be left at logic 0.
4PROTProtocol (PROT). Bit PROT is set if the protocol is T = 1
(asynchronous) and bit PROT = 0 if the protocol is T = 0.
3T/R Transmit/Receive (T/R). Bit T/R is set by software for transmission
mode. A change from logic 0 to 1 will set bit TBE in register USR.
Bit T/R is automatically reset by hardware if bit LCT has been used
before transmitting the last character.
2LCT Last Character to Transmit (LCT). Bit LCT is set by software before
writing the last character to be transmitted in the UTR. It allows
automatic change to reception mode. It is reset by hardware at the end
of a successful transmission. When LCT is being reset, the bit T/R is
also reset and the ISO 7816 UART is ready for receiving a character.
1SS Software convention Setting (SS). Bit SS is set by software before
ATR for automatic convention detection and early answer detection. It
is automatically reset by hardware at 10.5 ETU after reception of the
initial character.
0CONVConvention (CONV). Bit CONV is set if the convention is direct.
Bit CONV is either automatically written by hardware according to the
convention detected during ATR, or by software if the bit AUTOCONV
in register UCR2X is set.
Table 28. Register CCR1, CCR2 and CCR3 (address 01H; read and write)
[1]
7 6 5 4 3 2 1 0
CC7 CC6 SHL GST SC AC2 AC1 AC0
Table 29. Description of CCRx bits
Bit Symbol Description
7 CC7 not used
6 CC6 not used
5SHL Stop High or Low (SHL). If bit CST = 1, then the clock is
stopped at low level if bit SHL = 0, and at high level if
bit SHL = 1.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

TDA8007BHL/C4,118

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Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC 12bit 2-I/Os 5V
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