TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 40 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
[1] To meet these specifications, two ceramic multilayer capacitors with low ESR of minimum 100 nF should be used.
[2] Pin I/O1 has an integrated 14 k pull-up resistance to V
CC1
and pin I/O2 has an integrated 14 k pull-up resistance to V
CC2
.
[3] Pins C41 and C81 have an integrated 10 k pull-up resistance to V
CC1
and pins C42 and C82 have an integrated 10 k pull-up
resistance to V
CC2
.
[4] Pin I/OAUX has a 14 k pull-up resistance to V
DD
.
12. Timings
t
i(r)
, t
i(f)
input transition time (rise and fall time) C
L
=30pF - - 1.2 µs
Configured as output
V
OL
low-level output voltage I
OL
=1mA - - 300 mV
V
OH
high-level output voltage I
OH
= 40 mA 0.75V
DD
-V
DD
+0.25 V
t
o(r)
, t
o(f)
output transition time (rise and fall
time)
C
L
=30pF - - 0.1 µs
Interrupt line: pin INT
(open-drain output)
V
OH
low-level output voltage I
OH
=2mA - - 0.3 V
I
LIH
high-level input leakage current - - 10 µA
Table 35. Characteristics
…continued
V
DD
=3.3V; V
DDA
=3.3V; T
amb
= 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 36. Timings
V
DD
=3.3V; V
DDA
=3.3V; T
amb
= 25°C; unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Unit
Timing for non-multiplexed bus
Read control; see Figure 4
t
1
RD high to CS low 10 - - ns
t
2
access time CS low to data out valid - - 50 ns
t
3
CS high to data out (high) - - 10 ns
Write control; see Figure 5
and 6
t
4
data valid to end-of-write 10 - - ns
t
5
data hold time 10 - - ns
t
6
RD low to CS or WR low 10 - - ns
t
7
address stable to CS or WR high 10 - - ns
Timing for bit CRED
Read operations in UART receive register; see Figure 9
t
W(RD)
RD pulse width 10 - - ns
t
RD(URR)
RD low to bit CRED = 1 t
W(RD)
+2T
cy(CLK)
-t
W(RD)
+3T
cy(CLK)
ns
t
SB(FE)
set bit time FE 10.5 - - ETU
t
SB(RBF)
set time bit RBF 10.5 - - ETU
Write operations in UART transmit register; see Figure 10
t
W(WR)
WR pulse width 10 - - ns
t
WR(UTR)
WR low to I/O low t
W(WR)
+2T
cy(CLK)
-t
W(WR)
+3T
cy(CLK)
ns
Write operations in time-out configuration register; see Figure 11
t
W(WR)
WR pulse width 10 - - ns
