TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 7 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8. Functional description
Remark: Throughout this document, it is assumed that the reader is familiar with ISO7816
terminology.
8.1 Interface control
The TDA8007BHL/C3 is sensitive to ESD in functional mode. This sensitivity is seen on
pin ALE: an electrostatic discharge causes an edge on this pin and changes its mode of
communication. When the mode of communication is the multiplexed mode, this has no
impact. But when the mode used is the non-multiplexed mode, the ESD may change the
mode to multiplexed mode, which is irreversible without power-off/power-on.
The TDA8007BHL/C4 is an evolution of the C3 version in which the communication mode
is set to non-multiplexed and can not be changed.
8.1.1 Non-Multiplexed configuration
The TDA8007BHL/C4 is only in the non-multiplexed configuration (Figure 3), where the
TDA8007BHL/C3 offers a multiplexed configuration in addition to a non-mulitplexed
configuration. The configuration can be chosen through the ALE-pin. If pin ALE is tied to
V
DD
or ground, the TDA8007BHL/C3 will be in the non-multiplexed configuration.
The TDA8007BHL can be controlled via an 12-bit parallel bus (bits D0 to D7 and bits A0 to
A3). The address bits are determined by means of pins AD0 to AD3. The read or write
control signal is on pin RD and a data write or read active low enable signal is on pin WR.
Signals CS and WR play the same role.
In read operations (see Figure 4
) with signal RD = high, the data corresponding to the
chosen address is available on the bus when both signals CS and WR are low.
In write operations (see Figure 5
and 6) with signal RD = low, the data present on the bus
is written when signals CS and WR are low.
In both configurations, the TDA8007BHL/C4 is selected only when signal CS = low.
Signal INT
is an active low interrupt signal.
AD0 45 register selection address 0 input
XTAL2 46 connection for an external crystal
XTAL1 47 connection for an external crystal or input for an
external clock signal
DELAY 48 connection for an external delay capacitor
Table 3. Pin description
…continued
Symbol Pin Description
