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TDA8007BHL/C4,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 16 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
The time-out counter is very useful for processing the clock counting during ATR, the
Work Waiting Time (WWT) or the waiting times defined in protocol T = 1. It should be
noted that the 200 and n
max
clock counter (n
max
= 368 for TDA8007BHL/C4) used during
ATR is done by hardware when the start session is set, specific hardware controls the
functionality of BGT in T = 1 and T = 0 protocols and a specific register is available for
processing the extra guard time.
Writing to register TOC is not allowed as long as the card is not activated with a running
clock.
Before restarting the 16-bit counter (counters 3 and 2) by writing 61H, 65H, 71H, 75H,
F1H or F5H in the TOC; or the 24-bit counter (counters 3, 2 and 1) by writing 68H in the
TOC; it is mandatory to stop them by writing 00h in the TOC.
Detailed examples of how to use these specific timers can be found in application note
“AN01054”.
75H Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.
Counter 1 starts counting the content of register TOR1 on the first START bit
(reception or transmission) detected on pin I/O after 75H is written in register TOC.
When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
register USR is set, and the counter automatically restarts the same count until it is
stopped. Changing the content of register TOR1 during a count is not allowed.
Counting the value stored in registers TOR3 and TOR2 is started on the first START
bit detected on pin I/O (reception or transmission) after the value has been written,
and then on each subsequent START bit. It is possible to change the content of
registers TOR3 and TOR2 during a count; the current count will not be affected and
the new count value will be taken into account at the next START bit. The counter is
stopped by writing 00H in register TOC. In this configuration, registers TOR3, TOR2
and TOR1 must not be all zero.
7CH Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in
registers TOR3, TOR2 and TOR1 is started on the first START bit detected on pin I/O
(reception or transmission) after the value has been written, and then on each
subsequent START bit. It is possible to change the content of registers TOR3, TOR2
and TOR1 during a count; the current count will not be affected and the new count
value will be taken into account at the next START bit. The counter is stopped by
writing 00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1
must not be all zero.
85H Same as value 05H, except that all the counters will be stopped at the end of the 12th
ETU following the first received START bit detected after 85H has been written in
register TOC.
E5H Same configuration as value 65H, except that counter 1 will be stopped at the end of
the 12th ETU following the first START bit detected after E5H has been written in
register TOC.
F1H Same configuration as value 71H, except that the 16-bit counter will be stopped at the
end of the 12th ETU following the first START bit detected after F1H has been written
in register TOC.
F5H Same configuration as value 75H, except the two counters will be stopped at the end
of the 12th ETU following the first START bit detected after F5H has been written in
register TOC.
Table 12. Card registers (address 00h to F5h
…continued
Register Description
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 17 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.2 ISO UART registers
8.2.2.1 UART Transmit Register (UTR)
[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to transmit a character to the selected card, it writes the
data in direct convention in the UART transmit register. The transmission:
• Starts at the end of writing (on the rising edge of signal WR\) if the previous character
has been transmitted and if the extra guard time has expired
• Starts at the end of the extra guard time if this one has not expired
• Does not start if the transmission of the previous character is not completed
• With a synchronous card (bit SAN within register UCR2 is set), only signal D0 is
relevant and is copied on pin I/O of the selected card.
8.2.2.2 UART Receive Register (URR)
[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to read data from the card, it reads it from the UART
Receive Register (URR) in direct convention:
• With a synchronous card, only D0 is relevant and is a copy of the state of the selected
card I/O
• When needed, this register may be tied to a FIFO whose length ‘n’ is programmable
between 1 and 8; if n >1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
• With a parity error:
a. _ In protocol T = 0; the received byte is not stored in the FIFO and the error
counter is incremented. The error counter is programmable between 1 and 8.
When the programmed number is reached, then the bit PE is set in the status
register USR and INT0 falls low. The error counter must be reprogrammed to the
desired value after its count has been reached
b. _In protocol T = 1; the character is loaded in the FIFO and the bit PE is set
whatever the programmed value in the parity error counter
• When the FIFO is full, then the bit RBF in the status register USR is set. This bit is
reset when at least one character has been read from URR
• When the FIFO is empty, then the bit FE is set in the status register USR as long as
no character has been received.
Table 13. Register UTR (address 0DH; write only)
[1]
7 6 5 4 3 2 1 0
UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0
Table 14. Register URR (address 0DH; read only)
[1]
7 6 5 4 3 2 1 0
UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0
TDA8007BHL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9.1 — 18 June 2012 18 of 51
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
8.2.2.3 Mixed Status Register (MSR)
The MSR relates the status of pin INTAUX, the cards presence contacts PRES1
and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive
ready indicator TBE/RBF. It also gives useful indications when switching the clock to or
from 1/2 f
int
and when driving the TDA8007BHL/C4 with fast controllers.
No bits within register MSR act upon signal INT
.
[1] Register value at reset: bits TBE/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set
after reset.
Table 15. Register MSR (address 0Ch; read only)
[1]
7 6 5 4 3 2 1 0
CLKSW FE BGT CRED PR2 PR1 INTAUX TBE/RBF
Table 16. Description of MSR bits
Bit Symbol Description
7 CLKSW clock switch: Bit CLKSW is set when the TDA8007BHL/C4 has
performed a required clock switch from
1
⁄
n
f
XTAL
to ⁄
2
f
int
, and is reset
when the TDA8007BHL/C4 has performed a required clock switch from
1
⁄
2
f
int
to
1
⁄
n
f
XTAL
. The application must wait until this bit is set or reset
before sending a new command to the card. This bit is reset at
power-on.
6FE FIFO Empty: Bit FE is set when the reception FIFO is empty. It is reset
when at least one character has been loaded in the FIFO.
5BGT block guard time: In protocol T = 1, bit BGT is linked with a 22-ETU
counter which is started at every START bit on pin I/O. Bit BGT is set if
the count is finished before the next START bit. This helps to verify that
the card has not answered before 22 ETU after the last transmitted
character, or that the reader is not transmitting a character before
22 ETU after the last received character.
In protocol T = 0, bit BGT is linked with a 16-ETU counter which is
started at every START bit on pin I/O. Bit BGT is set if the count is
finished before the next START bit. This helps to verify that the reader
is not transmitting a character before 16 ETU after the last received
character.
4 CRED control ready: It is advised bit CRED is used for driving the
TDA8007BHL/C4 with high speed controllers. Before writing in
registers TOC or UTR, or reading from register URR, check if bit CRED
is set. If reset, it means that the writing or reading operation will not be
correct because the controller is acting faster than the required time for
this operation:
3PR2 card 2 present: Bit PR2 = 1 when card 2 is present.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

TDA8007BHL/C4,118

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Buy TDA8007BHL/C4,118
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC 12bit 2-I/Os 5V
Lifecycle:
New from this manufacturer.
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