SJA1000T/N1,118 Datasheet SJA1000T/N1,118, SJA1000T/N1,112, SJA1000/N1,112 | P16-P18

2000 Jan 04 16

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Notes

1. When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the

CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will

stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the

minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared

(bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if

enabled.

2. Errors detected during reception or transmission will affect the error counters according to the CAN 2.0B protocol

specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU

warning limit of 96. An error interrupt is generated, if enabled.

3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle.

4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit is set to

logic 1. The transmission complete status bit will remain at logic 0 (incomplete) until a message is transmitted

successfully.

5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is at logic 0 (locked), the written byte

will not be accepted and will be lost without being indicated.

6. When a message that shall be received has passed the acceptance filter successfully (i.e. earliest after arbitration

field), the CAN controller needs space in the RXFIFO to store the message descriptor. Accordingly there must be

enough space for each data byte which has been received. If there is not enough space to store the message, that

message will be dropped and the data overrun condition will be indicated to the CPU only, if this received message

has no errors until the last but one bit of end of frame (message becomes valid).

7. After reading a message stored in the RXFIFO and releasing this memory space with the command release receive

buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit

quantum (t

scl

2000 Jan 04 17

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

6.3.6 INTERRUPT REGISTER (IR)

The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the

INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating

level at INT. The interrupt register appears to the microcontroller as a read only memory.

Table 6 Bit interpretation of the interrupt register (IR); CAN address 3

Notes

1. Reading this bit will always reflect a logic 1.

2. A wake-up interrupt is also generated if the CPU tries to set go to sleep while the CAN controller is involved in bus

activities or a CAN interrupt is pending.

3. The overrun interrupt bit (if enabled) and the data overrun status bit are set at the same time.

4. The receive interrupt bit (if enabled) and the receive buffer status bit are set at the same time.

It should be noted that the receive interrupt bit is cleared upon a read access, even if there is another message

available within the FIFO. The moment the release receive buffer command is given and there is another message

valid within the receive buffer, the receive interrupt is set again (if enabled) with the next t

scl

BIT SYMBOL NAME VALUE FUNCTION

IR.7 −− − reserved; note 1

IR.6 −− − reserved; note 1

IR.5 −− − reserved; note 1

IR.4 WUI Wake-Up Interrupt;

note 2

1 set; this bit is set when the sleep mode is left

0 reset; this bit is cleared by any read access of the

microcontroller

IR.3 DOI Data Overrun Interrupt;

note 3

1 set; this bit is set on a ‘0-to-1’ transition of the data

overrun status bit, when the data overrun interrupt

enable is set to logic 1 (enabled)

0 reset; this bit is cleared by any read access of the

microcontroller

IR.2 EI Error Interrupt 1 set; this bit is set on a change of either the error

status or bus status bits if the error interrupt

enable is set to logic 1 (enabled)

0 reset; this bit is cleared by any read access of the

microcontroller

IR.1 TI Transmit Interrupt 1 set; this bit is set whenever the transmit buffer

status changes from logic 0 to logic 1 (released)

and transmit interrupt enable is set to logic 1

(enabled)

0 reset; this bit is cleared by any read access of the

microcontroller

IR.0 RI Receive Interrupt; note 4 1 set; this bit is set while the receive FIFO is not

empty and the receive interrupt enable bit is set

to logic 1 (enabled)

0 reset; this bit is cleared by any read access of the

microcontroller

2000 Jan 04 18

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

6.3.7 TRANSMIT BUFFER LAYOUT

The global layout of the transmit buffer is shown in Table 7. The buffer serves to store a message from the microcontroller

to be transmitted by the SJA1000. It is subdivided into a descriptor and data field. The transmit buffer can be written to

and read out by the microcontroller in operating mode only. In reset mode a ‘FFH’ is reflected for all bytes.

Table 7 Layout of transmit buffer

CAN

ADDRESS

FIELD NAME

BITS

76543210

10 descriptor identiﬁer byte 1 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3

11 identiﬁer byte 2 ID.2 ID.1 ID.0 RTR DLC.3 DLC.2 DLC.1 DLC.0

12 data TX data 1 transmit data byte 1

13 TX data 2 transmit data byte 2

14 TX data 3 transmit data byte 3

15 TX data 4 transmit data byte 4

16 TX data 5 transmit data byte 5

17 TX data 6 transmit data byte 6

18 TX data 7 transmit data byte 7

19 TX data 8 transmit data byte 8

6.3.7.1 Identiﬁer (ID)

The identifier consists of 11 bits (ID.10 to ID.0). ID.10 is

the most significant bit, which is transmitted first on the bus

during the arbitration process. The identifier acts as the

message’s name. It is used in a receiver for acceptance

filtering and also determining the bus access priority

during the arbitration process. The lower the binary value

of the identifier the higher the priority. This is due to a

larger number of leading dominant bits during arbitration.

6.3.7.2 Remote Transmission Request (RTR)

If this bit is set, a remote frame will be transmitted via the

bus. This means that no data bytes are included within this

frame. Nevertheless, it is necessary to specify the correct

data length code which depends on the corresponding

data frame with the same identifier coding.

If the RTR bit is not set, a data frame will be sent including

the number of data bytes as specified by the data length

code.

6.3.7.3 Data Length Code (DLC)

The number of bytes in the data field of a message is

coded by the data length code. At the start of a remote

frame transmission the data length code is not considered

due to the RTR bit being at logic 1 (remote). This forces

the number of transmitted/received data bytes to be

logic 0. Nevertheless, the data length code must be

specified correctly to avoid bus errors if two

CAN controllers start a remote frame transmission with the

same identifier simultaneously.

The range of the data byte count is 0 to 8 bytes and is

coded as follows:

DataByteCount = 8 × DLC.3 + 4 × DLC.2 + 2 × DLC.1 +

DLC.0

For reasons of compatibility no data length code >8 should

be used. If a value >8 is selected, 8 bytes are transmitted

in the data frame with the data length code specified in

DLC.

6.3.7.4 Data ﬁeld

The number of transferred data bytes is determined by the

data length code. The first bit transmitted is the most

significant bit of data byte 1 at address 12.

6.3.8 RECEIVE BUFFER

The global layout of the receive buffer is very similar to the

transmit buffer described in Section 6.3.7. The receive

buffer is the accessible part of the RXFIFO and is located

in the range between CAN address 20 and 29.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P68

SJA1000T/N1,118

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CAN Interface IC STAND ALONE CAN

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SJA1000T/N1,118

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