2000 Jan 04 59
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
10 AC CHARACTERISTICS
V
DD
=5V±10%; V
SS
=0V; C
L
= 50 pF (output pins); T
amb
= −40 to +125 °C; unless otherwise specified; note 1.
Notes
1. AC characteristics are not tested during production.
2. The analog input comparator may be bypassed internally using the CBP bit in the clock divider register, if external
transceiver circuitry is used. This results in reduced delays (<26 ns). V
I(RX)
= input voltage on pins RX0 and RX1.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
f
osc
oscillator frequency − 24 MHz
t
su(A-AL)
address set-up to ALE/AS LOW 8 − ns
t
h(AL-A)
address hold after ALE LOW 2 − ns
t
W(AL)
ALE/AS pulse width 8 − ns
t
RLQV
RD LOW to valid data output Intel mode − 50 ns
t
EHQV
E HIGH to valid data output Motorola mode − 50 ns
t
RHDZ
data float after RD HIGH Intel mode − 30 ns
t
ELDZ
data float after E LOW Motorola mode − 30 ns
t
DVWH
input data valid to WR HIGH Intel mode 8 − ns
t
WHDX
input data hold after WR HIGH Intel mode 8 − ns
t
WHLH
WR HIGH to next ALE HIGH 15 − ns
t
ELAH
E LOW to next AS HIGH Motorola mode 15 − ns
t
su(i)(D-EL)
input data set-up to E LOW Motorola mode 8 − ns
t
h(i)(EL-D)
input data hold after E LOW Motorola mode 8 − ns
t
LLWL
ALE LOW to WR LOW Intel mode 10 − ns
t
LLRL
ALE LOW to RD LOW Intel mode 10 − ns
t
LLEH
AS LOW to E HIGH Motorola mode 10 − ns
t
su(R-EH)
set-up time of RD/WR to E
HIGH
Motorola mode 5 − ns
t
W(W)
WR pulse width Intel mode 20 − ns
t
W(R)
RD pulse width Intel mode 40 − ns
t
W(E)
E pulse width Motorola mode 40 − ns
t
CLWL
CS LOW to WR LOW Intel mode 0 − ns
t
CLRL
CS LOW to RD LOW Intel mode 0 − ns
t
CLEH
CS LOW to E HIGH Motorola mode 0 − ns
t
WHCH
WR HIGH to CS HIGH Intel mode 0 − ns
t
RHCH
RD HIGH to CS HIGH Intel mode 0 − ns
t
ELCH
E LOW to CS HIGH Motorola mode 0 − ns
t
W(RST)
RST pulse width 100 − ns
Input comparator/output driver
t
SD
sum of input and output delays V
DD
=5V±10%;
V
DIF
= ±32 mV;
1.4V<V
I(RX)
<V
DD
− 1.4 V;
note 2
− 40 ns
