2000 Jan 04 7
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6 FUNCTIONAL DESCRIPTION
6.1 Description of the CAN controller blocks
6.1.1 INTERFACE MANAGEMENT LOGIC (IML)
The interface management logic interprets commands
from the CPU, controls addressing of the CAN registers
and provides interrupts and status information to the host
microcontroller.
6.1.2 TRANSMIT BUFFER (TXB)
The transmit buffer is an interface between the CPU and
the Bit Stream Processor (BSP) that is able to store a
complete message for transmission over the CAN
network. The buffer is 13 bytes long, written to by the CPU
and read out by the BSP.
6.1.3 RECEIVE BUFFER (RXB, RXFIFO)
The receive buffer is an interface between the acceptance
filter and the CPU that stores the received and accepted
messages from the CAN-bus line. The Receive Buffer
(RXB) representsa CPU-accessible 13-byte window of the
Receive FIFO (RXFIFO), which has a total length of
64 bytes.
With the help of this FIFO the CPU is able to process one
message while other messages are being received.
6.1.4 ACCEPTANCE FILTER (ACF)
The acceptance filter compares the received identifier with
the acceptance filter register contents and decides
whether this message should be accepted or not. In the
event of a positive acceptance test, the complete message
is stored in the RXFIFO.
6.1.5 BIT STREAM PROCESSOR (BSP)
The bit stream processor is a sequencer which controls the
data stream between the transmit buffer, RXFIFO and the
CAN-bus. It also performs the error detection, arbitration,
stuffing and error handling on the CAN-bus.
6.1.6 BIT TIMING LOGIC (BTL)
The bit timing logic monitors the serial CAN-bus line and
handles the bus line-related bit timing. It is synchronized to
the bit stream on the CAN-bus on a
‘recessive-to-dominant’ bus line transition at the beginning
of a message (hard synchronization) and re-synchronized
on further transitions during the reception of a message
(soft synchronization). The BTL also provides
programmable time segments to compensate for the
propagation delay times and phase shifts (e.g. due to
oscillator drifts) and to define the sample point and the
number of samples to be taken within a bit time.
6.1.7 ERROR MANAGEMENT LOGIC (EML)
The EML is responsible for the error confinement of the
transfer-layer modules. It receives error announcements
from the BSP and then informs the BSP and IML about
error statistics.
6.2 Detailed description of the CAN controller
The SJA1000 is designed to be software and
pin-compatible to its predecessor, the PCA82C200
stand-alone CAN controller. Additionally, a lot of new
functions are implemented. To achieve the software
compatibility, two different modes of operation are
implemented:
• BasicCAN mode; PCA82C200 compatible
• PeliCAN mode; extended features.
The mode of operation is selected with the CAN-mode bit
located within the clock divider register. Default mode
upon reset is the BasicCAN mode.
6.2.1 PCA82C200 COMPATIBILITY
In BasicCAN mode the SJA1000 emulates all known
registers from the PCA82C200 stand-alone CAN
controller. The characteristics, as described in Sections
6.2.1.1 to 6.2.1.4 are different from the PCA82C200
design with respect to software compatibility.
6.2.1.1 Synchronization mode
The SYNC bit in the control register is removed (CR.6 in
the PCA82C200). Synchronization is only possible by a
recessive-to-dominant transition on the CAN-bus. Writing
to this bit has no effect. To achieve compatibility to existing
application software, a read access to this bit will reflect
the previously written value (flip-flop without effect).
6.2.1.2 Clock divider register
The clock divider register is used to select the CAN mode
of operation (BasicCAN/PeliCAN). Therefore one of the
reserved bits within the PCA82C200 is used. Writing a
value between 0 and 7, as allowed for the PCA82C200,
will enter the BasicCAN mode. The default state is divide
by 12 for Motorola mode and divide by 2 for Intel mode.
An additional function is implemented within another of the
reserved bits. Setting of bit CBP (see Table 49) enables
the internal RX input comparator to be bypassed thereby
reducing the internal delays if an external transceiver
circuit is used.
