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SJA1000T/N1,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68
2000 Jan 04 31
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.6 INTERRUPT REGISTER (IR)
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN
interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except for the receive interrupt
bit.
The interrupt register appears to the CPU as a read only memory.
Table 15 Bit interpretation of the interrupt register (IR); CAN address 3
BIT SYMBOL NAME VALUE FUNCTION
IR.7 BEI Bus Error Interrupt 1 set; this bit is set when the CAN controller detects
an error on the CAN-bus and the BEIE bit is set
within the interrupt enable register
0 reset
IR.6 ALI Arbitration Lost Interrupt 1 set; this bit is set when the CAN controller lost the
arbitration and becomes a receiver and the ALIE
bit is set within the interrupt enable register
0 reset
IR.5 EPI Error Passive Interrupt 1 set; this bit is set whenever the CAN controller has
reached the error passive status (at least one
error counter exceeds the protocol-defined level of
127) or if the CAN controller is in the error passive
status and enters the error active status again and
the EPIE bit is set within the interrupt enable
register
0 reset
IR.4 WUI Wake-Up Interrupt;
note 1
1 set; this bit is set when the CAN controller is
sleeping and bus activity is detected and the
WUIE bit is set within the interrupt enable register
0 reset
IR.3 DOI Data Overrun Interrupt 1 set; this bit is set on a ‘0-to-1’ transition of the data
overrun status bit and the DOIE bit is set within
the interrupt enable register
0 reset
IR.2 EI Error Warning Interrupt 1 set; this bit is set on every change (set and clear)
of either the error status or bus status bits and the
EIE bit is set within the interrupt enable register
0 reset
IR.1 TI Transmit Interrupt 1 set; this bit is set whenever the transmit buffer
status changes from ‘0-to-1’ (released) and the
TIE bit is set within the interrupt enable register
0 reset
IR.0 RI Receive Interrupt; note 2 1 set; this bit is set while the receive FIFO is not
empty and the RIE bit is set within the interrupt
enable register
0 reset; no more message is available within the
RXFIFO
2000 Jan 04 32
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes
1. A wake-up interrupt is also generated, if the CPU tries to set the sleep bit while the CAN controller is involved in bus
activities or a CAN interrupt is pending.
2. The behaviour of this bit is equivalent to that of the receive buffer status bit with the exception, that RI depends on
the corresponding interrupt enable bit (RIE). So the receive interrupt bit is not cleared upon a read access to the
interrupt register. Giving the command ‘release receive buffer’ will clear RI temporarily. If there is another message
available within the FIFO after the release command, RI is set again. Otherwise RI remains cleared.
6.4.7 INTERRUPT ENABLE REGISTER (IER)
The register allows to enable different types of interrupt sources which are indicated to the CPU.
The interrupt enable register appears to the CPU as a read/write memory.
Table 16 Bit interpretation of the interrupt enable register (IER); CAN address 4
BIT SYMBOL NAME VALUE FUNCTION
IER.7 BEIE Bus Error Interrupt
Enable
1 enabled; if an bus error has been detected, the
CAN controller requests the respective interrupt
0 disabled
IER.6 ALIE Arbitration Lost Interrupt
Enable
1 enabled; if the CAN controller has lost arbitration,
the respective interrupt is requested
0 disabled
IER.5 EPIE Error Passive Interrupt
Enable
1 enabled; if the error status of the CAN controller
changes from error active to error passive or vice
versa, the respective interrupt is requested
0 disabled
IER.4 WUIE Wake-Up Interrupt
Enable
1 enabled; if the sleeping CAN controller wakes up,
the respective interrupt is requested
0 disabled
IER.3 DOIE Data Overrun Interrupt
Enable
1 enabled; if the data overrun status bit is set (see
status register; Table 14), the CAN controller
requests the respective interrupt
0 disabled
IER.2 EIE Error Warning Interrupt
Enable
1 enabled; if the error or bus status change (see
status register; Table 14), the CAN controller
requests the respective interrupt
0 disabled
IER.1 TIE Transmit Interrupt Enable 1 enabled; when a message has been successfully
transmitted or the transmit buffer is accessible
again (e.g. after an abort transmission command),
the CAN controller requests the respective
interrupt
0 disabled
IER.0 RIE Receive Interrupt
Enable; note 1
1 enabled; when the receive buffer status is ‘full’ the
CAN controller requests the respective interrupt
0 disabled
2000 Jan 04 33
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Note
1. The receive interrupt enable bit has direct influence to the receive interrupt bit and the external interrupt output INT.
If RIE is cleared, the external INT pin will become HIGH immediately, if there is no other interrupt pending.
6.4.8 ARBITRATION LOST CAPTURE REGISTER (ALC)
This register contains information about the bit position of losing arbitration. The arbitration lost capture register appears
to the CPU as a read only memory. Reserved bits are read as logic 0.
Table 17 Bit interpretation of the arbitration lost capture register (ALC); CAN address 11
On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At the same time, the current bit
position of the bit stream processor is captured into the arbitration lost capture register. The content within this register
is fixed until the users software has read out its contents once. The capture mechanism is then activated again.
The corresponding interrupt flag located in the interrupt register is cleared during the read access to the interrupt register.
A new arbitration lost interrupt is not possible until the arbitration lost capture register is read out once.
BIT SYMBOL NAME VALUE FUNCTION
ALC.7 to
ALC.5
− reserved For value and function see Table 18
ALC.4 BITNO4 bit number 4
ALC.3 BITNO3 bit number 3
ALC.2 BITNO2 bit number 2
ALC.1 BITNO1 bit number 1
ALC.0 BITNO0 bit number 0
Fig.5 Arbitration lost bit number interpretation.
handbook, full pagewidth
MGK619
ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR IDE
00
standard frame and
extended frame messages
extended frame
messages
01 02 03 04 05 06 07 08 09 10 11 12
ID.16 ID.15 ID.14 ID.13 ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4
14
ID.17
13
start of frame
15 16 17 18 19 20 21 22 23 24 25 26
ID.3 ID.2 ID.1 ID.0 RTR
27 28 29 30 31
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68

SJA1000T/N1,118

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Buy SJA1000T/N1,118
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC STAND ALONE CAN
Lifecycle:
New from this manufacturer.
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