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SJA1000T/N1,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68
2000 Jan 04 28
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.4 COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will
return a logic 0 when being read. Between two commands at least one internal clock cycle is needed in order to proceed.
The internal clock is half of the external oscillator frequency.
Table 13 Bit interpretation of the command register (CMR); CAN address 1
Notes
1. Upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to
the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also self test
mode in mode register).
2. Setting the command bits CMR.0 and CMR.1 simultaneously results in sending the transmit message once.
No re-transmission will be performed in the event of an error or arbitration lost (single-shot transmission).
Setting the command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the
self reception feature. No re-transmission will be performed in the event of an error or arbitration lost.
Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously results in sending the transmit message once
as described for CMR.0 and CMR.1.
The moment the transmit status bit is set within the status register, the internal transmission request bit is cleared
automatically.
Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
3. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the
data overrun status bit is set no further data overrun interrupt is generated.
4. After reading the contents of the receive buffer, the CPU can release this memory space in the RXFIFO by setting
the release receive buffer bit to logic 1. This may result in another message becoming immediately available within
the receive buffer. If there is no other message available, the receive interrupt bit is reset.
BIT SYMBOL NAME VALUE FUNCTION
CMR.7 − reserved −−
CMR.6 − reserved −−
CMR.5 − reserved −−
CMR.4 SRR Self Reception Request;
notes 1 and 2
1 present; a message shall be transmitted and
received simultaneously
0 − (absent)
CMR.3 CDO Clear Data Overrun;
note 3
1 clear; the data overrun status bit is cleared
0 − (no action)
CMR.2 RRB Release Receive Buffer;
note 4
1 released; the receive buffer, representing the
message memory space in the RXFIFO is
released
0 − (no action)
CMR.1 AT Abort Transmission;
notes 5 and 2
1 present; if not already in progress, a pending
transmission request is cancelled
0 − (absent)
CMR.0 TR Transmission Request;
notes 6 and 2
1 present; a message shall be transmitted
0 − (absent)
2000 Jan 04 29
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
5. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if
the original message has been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 or a transmit
interrupt has been generated.
It should be noted that a transmit interrupt is generated even if the message was aborted because the transmit buffer
status bit changes to ‘released’.
6. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic 1.
6.4.5 STATUS REGISTER (SR)
The content of the status register reflects the status of the CAN controller. The status register appears to the CPU as a
read only memory.
Table 14 Bit interpretation of the status register (SR); CAN address 2
BIT SYMBOL NAME VALUE FUNCTION
SR.7 BS Bus Status; note 1 1 bus-off; the CAN controller is not involved in bus
activities
0 bus-on; the CAN controller is involved in bus
activities
SR.6 ES Error Status; note 2 1 error; at least one of the error counters has
reached or exceeded the CPU warning limit
defined by the Error Warning Limit Register
(EWLR)
0 ok; both error counters are below the warning limit
SR.5 TS Transmit Status; note 3 1 transmit; the CAN controller is transmitting a
message
0 idle
SR.4 RS Receive Status; note 3 1 receive; the CAN controller is receiving a
message
0 idle
SR.3 TCS Transmission Complete
Status; note 4
1 complete; last requested transmission has been
successfully completed
0 incomplete; previously requested transmission is
not yet completed
SR.2 TBS Transmit Buffer Status;
note 5
1 released; the CPU may write a message into the
transmit buffer
0 locked; the CPU cannot access the transmit
buffer; a message is either waiting for
transmission or is in the process of being
transmitted
2000 Jan 04 30
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes
1. When the transmit error counter exceeds the limit of 255, the bus status bit is set to logic 1 (bus-off), the
CAN controller will set the reset mode bit to logic 1 (present) and an error warning interrupt is generated, if enabled.
The transmit error counter is set to 127 and the receive error counter is cleared. It will stay in this mode until the CPU
clears the reset mode bit. Once this is completed the CAN controller will wait the minimum protocol-defined time
(128 occurrences of the bus-free signal) counting down the transmit error counter. After that the bus status bit is
cleared (bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error warning interrupt
is generated, if enabled. Reading the TX error counter during this time gives information about the status of the
bus-off recovery.
2. Errors detected during reception or transmission will effect the error counters according to the CAN 2.0B protocol
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit (EWLR). An error warning interrupt is generated, if enabled. The default value of EWLR after hardware
reset is 96.
3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. If both bits are set the
controller is waiting to become idle again. After a hardware reset 11 consecutive recessive bits have to be detected
until the idle status is reached. After bus-off this will take 128 of 11 consecutive recessive bits.
4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit or the self
reception request bit is set to logic 1. The transmission complete status bit will remain at logic 0 until a message is
transmitted successfully.
5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is logic 0 (locked), the written byte
will not be accepted and will be lost without this being indicated.
6. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
space in the RXFIFO to store the message descriptor and for each data byte which has been received. If there is not
enough space to store the message, that message is dropped and the data overrun condition is indicated to the CPU
at the moment this message becomes valid. If this message is not completed successfully (e.g. due to an error), no
overrun condition is indicated.
7. After reading all messages within the RXFIFO and releasing their memory space with the command release receive
buffer this bit is cleared.
SR.1 DOS Data Overrun Status;
note 6
1 overrun; a message was lost because there was
not enough space for that message in the RXFIFO
0 absent; no data overrun has occurred since the
last clear data overrun command was given
SR.0 RBS Receive Buffer Status;
note 7
1 full; one or more complete messages are available
in the RXFIFO
0 empty; no message is available
BIT SYMBOL NAME VALUE FUNCTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68

SJA1000T/N1,118

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Buy SJA1000T/N1,118
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC STAND ALONE CAN
Lifecycle:
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