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SJA1000T/N1,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68
2000 Jan 04 49
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.16 RX MESSAGE COUNTER (RMC)
The RMC register (CAN address 29) reflects the number of messages available within the RXFIFO. The value is
incremented with each receive event and decremented by the release receive buffer command. After any reset event,
this register is cleared.
Table 42 Bit interpretation of the RX message counter (RMC); CAN address 29
Note
1. This bit cannot be written. During read-out of this register always a zero is given.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(0)
(1)
(0)
(1)
(0)
(1)
RMC.4 RMC.3 RMC.2 RMC.1 RMC.0
6.4.17 RX BUFFER STA RT ADDRESS REGISTER (RBSA)
The RBSA register(CAN address 30) reflects the currently
valid internal RAM address, where the first byte of the
received message, which is mapped to the receive buffer
window, is stored. With the help of this information it is
possible to interpret the internal RAM contents.
The internal RAM address area begins at CAN address 32
and may be accessed by the CPU for reading and writing
(writing in reset mode only).
Example: if RBSA is set to 24 (decimal), the current
message visible in the receive buffer window
(CAN address 16 to 28) is stored within the internal RAM
beginning at RAM address 24. Because the RAM is also
mapped directly to the CAN address space beginning at
CAN address 32 (equal to RAM address 0) this message
may also be accessed using CAN address 56 and the
following bytes
(CAN address = RBSA + 32 > 24 + 32 = 56).
If a message exceeds RAM address 63, it continues at
RAM address 0.
The release receive buffer command is always given while
there is at least one more message available within the
FIFO. RBSA is updated to the beginning of the next
message.
On hardware reset, this pointer is initialized to ‘00H’. Upon
a software reset (setting of reset mode) this pointer keeps
its old value, but the FIFO is cleared; this means that the
RAM contents are not changed, but the next received (or
transmitted) message will override the currently visible
message within the receive buffer window.
The RX buffer start address register appears to the CPU
as a read only memory in operating mode and as
read/write memory in reset mode. It should be noted that a
write access to RBSA takes effect first after the next
positive edge of the internal clock frequency, which is half
of the external oscillator frequency.
Table 43 Bit interpretation of the RX buffer start address register (RBSA); CAN address 30
Note
1. This bit cannot be written. During read-out of this register always a zero is given.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(0)
(1)
(0)
(1)
RBSA.5 RBSA.4 RBSA.3 RBSA.2 RBSA.1 RBSA.0
2000 Jan 04 50
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.5 Common registers
6.5.1 BUS TIMING REGISTER 0 (BTR0)
The contents of the bus timing register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW). This register can be accessed (read/write) if the reset mode is active.
In operating mode this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 44 Bit interpretation of bus timing register 0 (BTR0); CAN address 6
6.5.1.1 Baud Rate Prescaler (BRP)
The period of the CAN system clock t
scl
is programmable and determines the individual bit timing. The CAN system clock
is calculated using the following equation:
t
scl
=2×t
CLK
× (32 × BRP.5 + 16 × BRP.4 + 8 × BRP.3 + 4 × BRP.2 + 2 × BRP.1 + BRP.0 + 1)
where t
CLK
= time period of the XTAL frequency =
6.5.1.2 Synchronization Jump Width (SJW)
To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must
re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened or lengthened by one re-synchronization:
t
SJW
=t
scl
× (2 × SJW.1 + SJW.0 + 1)
6.5.2 BUS TIMING REGISTER 1 (BTR1)
The contents of bus timing register 1 defines the length of the bit period, the location of the sample point and the number
of samples to be taken at each sample point. This register can be accessed (read/write) if the reset mode is active.
In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 45 Bit interpretation of bus timing register 1 (BTR1); CAN address 7
6.5.2.1 Sampling (SAM)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0
BIT VALUE FUNCTION
SAM 1 triple; the bus is sampled three times; recommended for low/medium speed buses
(class A and B) where filtering spikes on the bus line is beneficial
0 single; the bus is sampled once; recommended for high speed buses (SAE class C)
1
f
XTAL
-------------
2000 Jan 04 51
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.5.2.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2)
TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point, where:
t
SYNCSEG
=1×t
scl
t
TSEG1
=t
scl
× (8 × TSEG1.3 + 4 × TSEG1.2 + 2 × TSEG1.1 + TSEG1.0 + 1)
t
TSEG2
=t
scl
× (4 × TSEG2.2 + 2 × TSEG2.1 + TSEG2.0 + 1)
Fig.13 General structure of a bit period.
handbook, full pagewidth
MGK628
t
TSEG2
t
TSEG1
t
SYNCSEG
t
scl
t
CLK
nominal bit time
SYNC
SEG
TSEG1 TSEG2 TSEG1
SYNC
SEG
sample point(s)
XTAL
CAN
Baud Rate Prescaler (BRP)
Possible values are BRP = 000001, TSEG1 = 0101 and TSEG2 = 010.
6.5.3 OUTPUT CONTROL REGISTER (OCR)
The output control register allows the set-up of different
output driver configurations under software control.
This register may be accessed (read/write) if the reset
mode is active. In operating mode, this register is read
only, if the PeliCAN mode is selected. In BasicCAN mode
a ‘FFH’ is reflected.
Table 46 Bit interpretation of the output control register (OCR); CAN address 8
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCMODE1 OCMODE0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P68

SJA1000T/N1,118

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Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC STAND ALONE CAN
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