2000 Jan 04 53
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.5.3.2 Clock output mode
For the TX0 pin this is the same as in normal output mode. However, the data stream to TX1 is replaced by the transmit
clock (TXCLK). The rising edge of the transmit clock (non-inverted) marks the beginning of a bit period. The clock pulse
width is 1 × t
scl
.
Fig.15 Example of clock output mode.
handbook, full pagewidth
MGK630
1 bit time
HIGH
HIGH
LOW
LOW
TX0
TX1
6.5.3.3 Bi-phase output mode
In contrast to the normal output mode the bit
representation is time variant and toggled. If the bus
controllers are galvanically decoupled from the bus line by
a transformer, the bit stream is not allowed to contain a
DC component. This is achieved by the following scheme.
During recessive bits all outputs are deactivated (floating).
Dominant bits are sent with alternating levels on TX0 and
TX1, i.e. the first dominant bit is sent on TX0, the second
is sent on TX1, and the third one is sent on TX0 again, and
so on. One possible configuration example of the bi-phase
output mode timing is shown in Fig.16.
