OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ZL50052GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
ZL50052 Data Sheet
10
Zarlink Semiconductor Inc.
FP16o P12
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control Register is LOW
(default), this pin outputs a 61 ns-wide frame pulse. When the FPW bit is
HIGH, this pin outputs a 122 ns-wide frame pulse. The frame pulse, running
at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input
frame pulse (FP8i
). Output data on both the Backplane and Local sides
(BSTo0-7 and LSTo0-7) will be aligned to this frame pulse and the
accompanying output clock, C16o
.
Backplane and Local Inputs
BSTi0-7 G1, H1, H2, H3,
J1, J2, K1, J3
Backplane Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal
Pull-downs)
These pins accept serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
LSTi0-7 K14, J13, J14,
K13, M14, J12,
L14, M13
Local Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal
Pull-downs)
These pins accept serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Backplane and Local Outputs and Control
ODE B9 Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
An asynchronous input providing Output Enable control to the BSTo0-7 and
LSTo0-7 outputs.
When LOW, the BSTo0-7 and LSTo0-7 outputs are driven HIGH or high
impedance (dependent on the BORS and LORS pin settings respectively).
When HIGH, the outputs BSTo0-7 and LSTo0-7 are enabled.
BORS G2 Backplane Output Reset State (5 V Tolerant Input with Internal
Pull-down)
When this input is LOW, the device will initialize with the BSTo0-7 outputs
driven high. Following initialization, the Backplane stream outputs are always
active.
When this input is HIGH, the device will initialize with the BSTo0-7 outputs at
high impedance. Following initialization, the Backplane stream outputs may
be set active or high impedance using the ODE pin or on a per-channel basis
with the BE bit in the Backplane Connection Memory.
BSTo0-7 B3, A1, A2, C4,
C5, B2, D2, C2
Backplane Serial Output Streams 0 to 7 (5 V Tolerant, Three-state
Outputs with Slew-Rate Control)
These pins output serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Refer to the descriptions of the BORS and ODE pins for control of the output
HIGH or high impedance state.
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description
ZL50052 Data Sheet
11
Zarlink Semiconductor Inc.
LORS H13 Local Output Reset State (5 V Tolerant Input with Internal Pull-down)
When this input is LOW, the device will initialize with the LSTo0-7 outputs
driven high. Following initialization, the Local stream outputs are always
active.
When this input is HIGH, the device will initialize with the LSTo0-7 outputs at
high impedance. Following initialization, the Local stream outputs may be set
active or high impedance using the ODE pin or on a per-channel basis with
the LE bit in the Local Connection Memory.
LSTo0-7 B13, B14, D14,
C14, D12, E14,
D13, E13
Local Serial Output Streams 0 to 7 (5 V Tolerant Three-state Outputs
with Slew-Rate Control)
These pins output serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Refer to the descriptions of the LORS and ODE pins for control of the output
HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14 B1, B4, B5, D5,
A3, A4, C6, B6,
A5, A6, C7, B7,
A7, A8, B8
Address 0 - 14 (5 V Tolerant Inputs)
These pins form the 15-bit address bus to the internal memories and
registers.
A0 = LSB
D0 - D15 N7, P7, P6, N6,
P5, M6, P4, N5,
P3, P2, N3, N4,
M5, N2, M4, M3
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control)
These pins form the 16-bit data bus of the microprocessor port.
D0 = LSB
CS
A10 Chip Select (5 V Tolerant Input)
Active LOW input used by the microprocessor to enable the microprocessor
port access
Note that a minimum of 30 ns must separate the de-assertion of DTA
(to
high) and the assertion of CS
and/or DS to initiate the next access.
DS
C8 Data Strobe (5 V Tolerant Input)
This active LOW input works in conjunction with CS
to enable the
microprocessor port read and write operations.
Note that a minimum of 30 ns must separate the de-assertion of DTA
(to
high) and the assertion of CS
and/or DS to initiate the next access.
R/W
A9 Read/Write (5 V Tolerant Input)
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
DTA
D9 Data Transfer Acknowledgment (5 V Tolerant Three-state Output)
This active LOW output indicates that a data bus transfer is complete. A
pull-up resistor is required to hold a HIGH level.
Note that a minimum of 30 ns must separate the de-assertion of DTA
(to
high) and the assertion of CS
and/or DS to initiate the next access.
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description
ZL50052 Data Sheet
12
Zarlink Semiconductor Inc.
RESET C9 Device Reset (5 V Tolerant Input with Internal Pull-up)
This input (active LOW) asynchronously applies reset and synchronously
releases reset to the device. In the reset state, the outputs LSTo0-7 and
BSTo0-7 are set to a HIGH or high impedance state, depending on the state
of the LORS and BORS external control pins, respectively. The assertion of
this pin also clears the device registers and internal counters. Refer to
Section 7.3 on page 24 for the timing requirements regarding this reset
signal.
JTAG Control Signals
TCK B11 Test Clock (5 V Tolerant Input)
Provides the clock to the JTAG test logic.
TMS A11 Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
TDi B10 Test Serial Data In (5 V Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
TDo A12 Test Serial Data Out (5 V Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK. This pin is
held in a high impedance state when JTAG is not enabled.
TRST
A14 Test Reset (5 V Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset
state. This pin must be pulsed LOW during power-up for JTAG testing. This
pin must be held LOW for normal functional operation of the device.
Power and Ground Pins
V
DD_IO
D6, D7, D8,
D10, E4, E11,
F4, F11, G4,
G11, H4, H11,
J4, J11, K4, K11,
L5, L6, L7, L8,
L9, L10
Power Supply for Periphery Circuits: +3.3 V
V
DD_CORE
E6, E7, E8, E9,
F5, F10, G3, G5,
G10, H5, H10,
H12, J5, J10,
K6, K7, K8, K9
Power Supply for Core Circuits: +1.8 V
V
DD_PLL
N9
Power Supply for Analog PLL: +1.8 V
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

ZL50052GAC

Mfr. #:
Buy ZL50052GAC
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet