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ZL50052GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
ZL50052 Data Sheet
22
Zarlink Semiconductor Inc.
5.0 Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. Channels written
to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit
advancement have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), and output channel number (n). For 32.768 Mbps data rate, there are 512 channels on each
stream. The input channel number (m) and output channel number (n) can therefore have a range of 0 to 511. The
data throughput delay under various input channel and output channel conditions can be summarized as:
T = 2 frames + (n - m)
The data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel)
are equal, we have the figure below, in which the delay between the input data being written and the output data
being read is exactly 2 frames.
Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0
110X1HI-Z
11100HIGH
11101HI-Z
1111XACTIVE
(HIGH or LOW)
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-7/
BSTo0-7
Table 1 - Local and Backplane Output Enable Control Priority (continued)
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + 0
ZL50052 Data Sheet
23
Zarlink Semiconductor Inc.
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.
Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
6.0 Microprocessor Port
The 8 K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS
, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 4,096 locations. See Table 5, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA
handshake when accessed, but any data read from the bus will be invalid.
7.0 Device Power-Up, Initialization and Reset
7.1 Power-Up Sequence
The recommended power-up sequence is for the V
DD_IO
supply (nominally +3.3 V) to be established before the
power-up of the V
DD_PLL
and V
DD_CORE
supplies (nominally +1.8 V). The V
DD_PLL
and V
DD_CORE
supplies may be
powered-up simultaneously, but neither should 'lead' the V
DD_IO
supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + (n - m)
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + (n - m)
ZL50052 Data Sheet
24
Zarlink Semiconductor Inc.
7.2 Initialization
Upon power-up, the device should be initialized by applying the following sequence:
7.3 Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-7 and BSTo0-7 are set to HIGH or high impedance, and all internal registers and
counters are reset to the default state.
The RESET
pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250 µs must also be waited before the first microprocessor access is performed following
the de-assertion of the RESET
pin; this delay is required for determination of the frame pulse format.
In addition, the reset signal must be de-asserted less than 12 µs after the frame boundary or more than 13µs after
the frame boundary, as illustrated in Figure 14. This can be achieved, for example, by synchronizing the
de-assertion of the reset signal with the input frame pulse FP8i
.
Figure 14 - Hardware RESET
De-assertion
1 Ensure the TRST
pin is permanently LOW to disable the JTAG TAP controller.
2Set ODE pin to LOW. This sets the LSTo0-7 outputs to HIGH or high impedance, dependent on the
LORS input value, and sets the BSTo0-7 outputs to HIGH or high impedance, dependent on BORS
input value. Refer to Pin Description for details of the LORS and BORS pins.
3 Reset the device by asserting the RESET
pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250 µs must also be applied before the first microprocessor access is
performed following the de-assertion of the RESET
pin; this delay is required for determination of the
input frame pulse format.
4 Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 8.3, Connection Memory Block Programming.
5Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
FP8i
RESET
12 µs
13 µs
De-assertion of RESET
must not fall within this window
RESET
assertion
RESET de-assertion
RESET
(case 1)
(case 2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

ZL50052GAC

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Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
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