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ZL50052GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
ZL50052 Data Sheet
52
Zarlink Semiconductor Inc.
Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps)
CK_int *
FP8i
C8i
L/BSTi0-7
L/BSTo0-7
t
IDS32
32.768 Mbps
32.768 Mbps
t
SIH32
t
SIS32
t
SOD32
Bit0
Ch0
Bit1
Ch0
Bit6
Ch511
Bit7
Ch511
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
6
5
0
4
3
2
1
7
Note *:
CK_int is the internal clock signal of 131.072 MHz.
2
Bit5
Ch511
CK_int *
FP8
o
C8o
t
OFBOS
ZL50052 Data Sheet
53
Zarlink Semiconductor Inc.
Note 1: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge
C
L
.
Figure 21 - Serial Output and External Control
Figure 22 - Output Driver Enable (ODE)
Local and Backplane Output High-Impedance Timing
Characteristic Sym. Min. Typ. Max. Units Test Conditions
1 STo delay - Active to High-Z
- High-Z to Active
t
DZ
t
ZD
4
4
6
6
ns
ns
R
L
=1k, C
L
= 50 pF, See Note 1
2 Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to High-Impedance
t
ODE
t
ODZ
14
14
ns
ns
R
L
=1k, C
L
= 50 pF, See Note 1
R
L
1k, C
L
= 50 pF, See Note 1
t
DZ
STo
t
ZD
STo
CLK
VTT
VTT
HiZ
Valid Data
VTT
HiZ
Valid Data
VTT
Hi-Z
Hi-Z
STo
ODE
t
ODZ
t
ODE
Valid Data
VTT
ZL50052 Data Sheet
54
Zarlink Semiconductor Inc.
Input Clock Jitter Tolerance
Jitter Frequency
32.768 Mbps Data Rate
Jitter Tolerance
Units
1 1 kHz 600 ns
2 10 kHz 600 ns
3 50 kHz 80 ns
4 66 kHz 50 ns
5 83 kHz 35 ns
6 95 kHz 30 ns
7100 kHz 20 ns
8200 kHz 14 ns
9300 kHz 14 ns
10 400 kHz 14 ns
11 500 kHz 14 ns
12 1 MHz 14 ns
13 2 MHz 14 ns
14 4 MHz 14 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

ZL50052GAC

Mfr. #:
Buy ZL50052GAC
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
Lifecycle:
New from this manufacturer.
Delivery:
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