ZL50052 Data Sheet
55
Zarlink Semiconductor Inc.
Note 1: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge
C
L
.
Note 2: There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30 ns must separate the de-assertion of DTA
(to high) and the assertion of CS and/or DS to initiate the next
access).
Non-Multiplexed Microprocessor Port Timing
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1CS
setup from DS falling t
CSS
0ns
2R/W
setup from DS falling t
RWS
9ns
3 Address setup from DS
falling t
ADS
9ns
4CS
hold after DS rising t
CSH
0ns
5R/W
hold after DS rising t
RWH
9ns
6 Address hold after DS
rising t
ADH
9ns
7 Data setup from DTA
Low on Read t
RDS
5
12
ns
ns
Memory Read
Register Read
C
L
=60pF
8 Data hold on read t
RDH
4.5 ns C
L
=60pF,
R
L
=1k
Note 1
9 Data setup on write t
WDS
9ns
10 Data hold on write t
WDH
9ns
11 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
t
AKD
88
80
ns
ns
C
L
=60pF
C
L
=60pF
12 Acknowledgment Hold Time t
AKH
11 ns C
L
=60pF,
R
L
=1k,
Note 1
