ZL50052 Data Sheet
42
Zarlink Semiconductor Inc.
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR7)
Addresses 00A3
H
to 00AA
H
8 Backplane Output Advancement Registers (BOAR0 to BOAR7) allow users to program the output advancement
for output data streams BSTo0 to BSTo7. The possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of
the internal system clock (131.072 MHz).
The BOAR0 to BOAR7 registers are configured as follows:
Table 19 - Backplane Output Advancement Register (BOAR) Bits
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o
.
BOARn Bit
(where n = 0 to 7)
Name
Reset
Value
Description
15:2 Reserved 0 Reserved
Must be set to 0 for normal operation
1:0 BOA[1:0] 0 Backplane Output Advancement Value
Backplane Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz BOA1 BOA0
0 (Default) 0 0
-1 cycle (~7.6 ns) 0 1
-2 cycles (~15 ns) 1 0
-3 cycles (~23 ns) 1 1
Table 20 - Backplane Output Advancement (BOAR) Programming Table
