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ZL50052GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
ZL50052 Data Sheet
28
Zarlink Semiconductor Inc.
10.2.2.3 The Device Identification Register
The JTAG device ID for the ZL50052 is 0C38414B
H
.
Version, Bits <31:28>: 0000
Part No., Bits <27:12>: 1100 0011 1000 0100
Manufacturer ID, Bits <11:1>: 0001 0100 101
Header, Bit <0> (LSB): 1
10.3 Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
11.0 Memory Address Mappings
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
Table 5 - Address Map for Data and Connection Memory Locations (A14 = 1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
Address Bit Description
A14 Selects memory or register access (0 = register, 1 = memory)
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
A13-A9 Stream address (0 - 7)
Streams 0 to 7 are used
A8-A0 Channel address (0 - 511)
Channels 0 to 511 are used when serial stream is at 32.768 Mbps
ZL50052 Data Sheet
29
Zarlink Semiconductor Inc.
11.1 Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
11.2 Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane
input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the
addresses of the streams and the channels. The BDM is read-only and configured as follows:
Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
11.3 Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 8 for Source-to-Local connections.
The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or
Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the
LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-7) in place of data defined by the
Source Control, Stream and Channel Address bits.
Bit Name Description
15:8 Reserved Set to a default value of 8’h00.
7:0 LDM Local Data Memory - Local Input Channel Data
The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, e.g., bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 6, “ST-BUS and GCI-Bus Input Timing
Diagram” for the arrival order of the bits.
Table 6 - Local Data Memory (LDM) Bits
Bit Name Description
15:8 Reserved Set to a default value of 8’h00.
7:0 BDM Backplane Data Memory - Backplane Input Channel Data.
The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM
stream. BDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 6, “ST-BUS and GCI-Bus Input Timing
Diagram” for the arrival order of the bits.
Table 7 - Backplane Data Memory (BDM) Bits
ZL50052 Data Sheet
30
Zarlink Semiconductor Inc.
11.4 Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 4,096 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit
definition for each 16-bit word is presented in Table 9 for Source-to-Backplane connections.
The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or
Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower
byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-7) in place of data
defined by the Source Control, Stream and Channel Address bits.
Bit Name Description
15 LSRC Local Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14 LMM Local Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).
13 LE Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.
12:9 LSAB[3:0] Source Stream Address Bits
The binary value of these 4 bits represents the input stream number.
Ignored when LMM is set HIGH.
8:0 LCAB[8:0] Source Channel Address Bits / Message Mode Data
The binary value of these 9 bits represents the input channel number, when LMM is LOW.
Bits LCAB[7:0] transmitted as data when LMM is set HIGH.
Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are
output sequentially to the timeslot with LCAB[7] being output first.
Table 8 - LCM Bits for Source-to-Local Switching
Bit Name Description
15 BSRC Backplane Source Control Bit
When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.
14 BMM Backplane Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Backplane or Local Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Backplane Connection Memory).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

ZL50052GAC

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Digital Bus Switch ICs
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