ZL50052 Data Sheet
47
Zarlink Semiconductor Inc.
15.0 AC Electrical Characteristics
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
Characteristics Sym. Level Units Conditions
1CMOS Threshold V
CT
0.5 V
DD_IO
V 3.0 V < V
DD_IO
< 3.6 V
2 Rise/Fall Threshold Voltage High V
HM
0.7 V
DD_IO
V 3.0 V < V
DD_IO
< 3.6 V
3 Rise/Fall Threshold Voltage Low V
LM
0.3 V
DD_IO
V 3.0 V < V
DD_IO
< 3.6 V
Input and Output Clock Timing
Characteristic Sym. Min. Typ. Max. Units Notes
1FP8i
, Input Frame Pulse Width t
IFPW244
t
IFPW122
210
10
244
122
350
220
ns
2 Input Frame Pulse Setup Time
(before C8i
clock falling/rising edge)
t
IFPS244
t
IfPS122
5
5
110
60
ns
3 Input Frame Pulse Hold Time
(from C8i
clock falling/rising edge)
t
IFPH244
t
IFPH122
0
0
110
60
ns
4C8i
Clock Period (Average value, does not
consider the effects of jitter)
t
ICP
120 122 124 ns
5C8i Clock Pulse Width High t
ICH
50 61 70 ns
6C8i
Clock Pulse Width Low t
ICL
50 61 70 ns
7C8i
Clock Rise/Fall Time t
rIC
, t
fIC
023ns
8C8i
Cycle to Cycle Variation
(This values is with respect to the typical
C8i
Clock Period, and using mid-bit
sampling)
t
CCVIC
-7.0 7.0 ns
9 Output Frame Boundary Offset t
OFBOS
79.5ns
10 FP8o
Frame Pulse Width t
OFPW8_244
t
OFPW8_122
224
117
244
122
264
127
ns FPW = 1
FPW = 0
C
L
=60pF
11 FP8o
Output Delay
(from frame pulse edge to output frame
boundary)
t
FPFBF8_244
t
FPFBF8_122
117
58
122
61
127
64
ns FPW = 1
FPW = 0
C
L
=60pF
12 FP8o
Output Delay
(from output frame boundary to frame pulse
edge)
t
FBFPF8_244
t
FBFPF8_122
117
58
122
61
127
64
ns FPW = 1
FPW = 0
C
L
=60pF
13 C8o
Clock Period t
OCP8
117 122 127 ns
C
L
=60pF
14 C8o
Clock Pulse Width High t
OCH8
58 61 64 ns
15 C8o
Clock Pulse Width Low t
OCL8
58 61 64 ns
16 C8o
Clock Rise/Fall Time t
rOC8
, t
fOC8
37ns
