ZL50052 Data Sheet
43
Zarlink Semiconductor Inc.
13.7 Memory BIST Register
Address 014D
H
.
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
Bit Name
Reset
Value
Description
15:13 Reserved 0 Reserved
Must be set to 0 for normal operation
12 LV_TM 0 MBIST Test Enable
Set HIGH to enable MBIST mode.
Set LOW for normal operation.
11 BISTSDB 0 Backplane Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
10 BISTCDB 0 Backplane Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane Data
Memory BIST sequence.
9BISTPDB 0 Backplane Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Data Memory BIST sequence (indicated by assertion of BISTCDB).
A HIGH indicates Pass, a LOW indicates Fail.
8BISTSDL 0Local Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
7 BISTCDL 0 Local Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Data
Memory BIST sequence.
6BISTPDL 0Local Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local Data
Memory BIST sequence (indicated by assertion of BISTCDL).
A HIGH indicates Pass, a LOW indicates Fail.
5BISTSCB 0 Backplane Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
4 BISTCCB 0 Backplane Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane
Connection Memory BIST sequence.
3BISTPCB 0 Backplane Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Connection Memory BIST sequence (indicated by assertion of BISTCCB).
A HIGH indicates Pass, a LOW indicates Fail.
Table 21 - Memory BIST Register (MBISTR) Bits
