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ZL50052GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
ZL50052 Data Sheet
19
Zarlink Semiconductor Inc.
When SMPL_MODE = LOW (input bit fractional delay mode) , bits LID[4:0] and BID[4:0] in the LIDR0 - 7 and
BIDR0 - 7 registers respectively define the input bit fractional delay of the corresponding Local and Backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 8 for Input Bit Delay Timing at 32 Mbps data rates.
Refer to Figure 9 for Input Sampling Point Selection Timing at 32 Mbps data rates.
Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32 Mbps
C8i
72345610
BSTi/LSTi0-7
Bit Delay = 0
Ch0
7456
Ch1
2310
BSTi/LSTi0-7
Bit Delay = 1/4
72345610
BSTi/LSTi0-7
Bit Delay = 1
Ch0
756
Ch1
2310
(Default)
72345610
Ch0
7456
Ch1
2310
Ch511
Ch511
Ch511
Bit Delay, 1/4
Bit Delay, 1
BSTi/LSTi0-7
Bit Delay = 1/2
72345610
Ch0
7456
Ch1
2310
Ch511
Bit Delay, 1/2
BSTi/LSTi0-7
Bit Delay = 3/4
72345610
Ch0
7456
Ch1
2310
Ch511
Bit Delay, 3/4
BSTi/LSTi0-7
Bit Delay = 7 1/2
72345610
Ch511
7456
Ch0
210
Ch510
Bit Delay, 7 1/2
BSTi/LSTi0-7
Bit Delay = 7 3/4
72345610
Ch511
7456
Ch0
210
Ch510
Bit Delay, 7 3/4
FP8i
SMPL_MODE = LOW
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
ZL50052 Data Sheet
20
Zarlink Semiconductor Inc.
Figure 9 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
Data Rate of 32 Mbps
3.2 Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o
. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR7 and BOAR0 - BOAR7, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072 MHz). The advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which
converts to approximately 0 ns, -7.6 ns, -15 ns or -23 ns as shown in Figure 10.
C8i
7
2
3
4
56
BSTi/LSTi0-7
BID[4:0]/LID[4:0] = 00011
B
Ch0
1
0
Ch511
sample at 3/4 point
FP8i
7
2
3
4
56
BSTi/LSTi0-7
BID[4:0]/LID[4:0] = 00000
B
Ch0
1
0
Bit delay = 0 bit (Default)
Ch511
sample at 3/4 point
SMPL_MODE = LOW
C8i
7
2
3
4
56
BSTi/LSTi0-7
BID[4:0]/LID[4:0] = 00011
B
Ch0
1
0
Ch511
sample at 2/4 point
FP8i
7
2
3
4
56
BSTi/LSTi0-7
BID[4:0]/LID[4:0] = 00000
B
Ch0
1
0
3/4 sampling (Default)
Ch511
sample at 3/4 point
SMPL_MODE = HIGH
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Bit Delay = 3/4 bit
2/4 sampling
ZL50052 Data Sheet
21
Zarlink Semiconductor Inc.
Figure 10 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 32 Mbps
4.0 Port High-Impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-7) and Backplane (BSTo0-7) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-7/BSTo0-7, to transmit bi-state
channel data.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-7/BSTo0-7, of the device to invoke
a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-7. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See “Local Connection
Memory Bit Definition”, on page 29 and “Backplane Connection Memory Bit Definition”, on page 30 for
programming details.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET
operation,
e.g., following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET
, ODE, OSB, LE/BE.
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-7/
BSTo0-7
0XXX0HIGH
0XXX1HI-Z
10XX0HIGH
10XX1HI-Z
110X0HIGH
Table 1 - Local and Backplane Output Enable Control Priority
Bit Advancement, -1
Bit Advancement, -2
Bit Advancement, -3
FP8o
System Clock
BSTo/LSTo0-7
Bit Advancement = 0
BSTo/LSTo0-7
Bit Advancement = -1
(Default)
Bit Advancement = -3
BSTo/LSTo0-7
Bit Advancement = -2
BSTo/LSTo0-7
131.072 MHz
Ch511
Ch511
Ch511
Ch511
Ch0
Ch0
Ch0
Ch0
Bit 1
Bit 0 Bit 7 Bit 6 Bit 5
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1
Bit 0 Bit 7 Bit 6 Bit 5
Bit 1
Bit 0 Bit 7 Bit 6 Bit 5
Bit 4
Bit 4
Bit Advancement, 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

ZL50052GAC

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Buy ZL50052GAC
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
Lifecycle:
New from this manufacturer.
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