OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AT91SAM9G45B-CU-999

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
13
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
C15 D2 H6 PE7 M15 DDR_D14 U6 PB17
C16 GNDIOM H7 PE9 M16 DDR_D15 U7 PD7
C17 A18 H8 PE10 M17 DDR_A0 U8 PD10
C18 A12 H9 GNDCORE M18 DDR_A2 U9 PD14
D1 XOUT32 H10 GNDIOP N1 PA3 U10 TCK
D2 PD20 H11 VDDCORE N2 PA9 U11 VDDOSC
D3 GNDBU H12 GNDIOM N3 PA12 U12 GNDOSC
D4 VDDBU H13 GNDIOM N4 PA15 U13 PB10
D5 PC24 H14 DDR_CS N5 PA16 U14 PB26
D6 PC18 H15 DDR_WE N6 PA17 U15 HHSDPB/DHSDP
D7 PC13 H16 DDR_DQM1 N7 PB18 U16 HHSDMB/DHSDM
D8 PC6 H17 DDR_CAS N8 PD6 U17 GNDUTMI
D9 NWR1/NBS1 H18 DDR_NCLK N9 PD16 U18 VDDUTMIC
D10 NANDOE J1 PE19 N10 NTRST V1 PA31
D11 DQM1 J2 PE16 N11 PB9 V2 PB1
D12 D14 J3 PE14 N12 PB24 V3 PB2
D13 D9 J4 PE15 N13 PB28 V4 PB5
D14 D5 J5 PE12 N14 DDR_D13 V5 PB15
D15 D1 J6 PE17 N15 DDR_D8 V6 PD3
D16 VDDIOM1 J7 PE18 N16 DDR_D9 V7 PD5
D17 A11 J8 PE20 N17 DDR_D11 V8 PD12
D18 A10 J9 GNDCORE N18 DDR_D12 V9 PD17
E1 PD21 J10 GNDCORE P1 PA11 V10 TDO
E2 TSADVREF J11 GNDIOP P2 PA13 V11 XOUT
E3 VDDANA J12 GNDIOM P3 PA19 V12 XIN
E4 JTAGSEL J13 GNDIOM P4 PA21 V13 VDDPLLUTMI
E5 TST J14 DDR_A12 P5 PA23 V14 VDDIOP2
E6 PC23 J15 DDR_A13 P6 PB12 V15 HFSDPB/DFSDP
E7 PC16 J16 DDR_CKE P7 PB19 V16 HFSDMB/DFSDM
E8 PC8 J17 DDR_RAS P8 PD8 V17 VDDUTMII
E9 PC1 J18 DDR_CLK P9 PD28 V18 VBG
Table 4-1. SAM9G45 Pinout for 324-ball BGA Package (Continued)
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
14
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
5. Power Considerations
5.1 Power Supplies
The SAM9G45 has several types of power supply pins:
z VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage
ranges from 0.9V to 1.1V, 1.0V typical.
z VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical).
z VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V and 1.95V (1.8V
typical) or between 3.0V and 3.6V (3.3V typical).
z VDDIOP0, VDDIOP1, VDDIOP2 pins: Power the Peripherals I/O lines; voltage ranges from 1.65V to 3.6V.
z VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the System Controller;
voltage ranges from 1.8V to 3.6V.
z VDDPLLUTMI pin: Powers the PLLUTMI cell; voltage range from 0.9V to 1.1V.
z VDDUTMIC pin: Powers the USB device and host UTMI+ core; voltage range from 0.9V to 1.1V, 1.0V typical.
z VDDUTMII pin: Powers the USB device and host UTMI+ interface; voltage range from 3.0V to 3.6V, 3.3V typical.
z VDDPLLA pin: Powers the PLLA cell; voltage ranges from 0.9V to 1.1V.
z VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V
z VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V typical.
Some supply pins share common ground (GND) pins whereas others have separate grounds.
The respective power/ground pin assignments are as follows:
VDDCORE GNDCORE
VDDIOM0, VDDIOM1 GNDIOM
VDDIOP0, VDDIOP1, VDDIOP2 GNDIOP
VDDBU GNDBU
VDDUTMIC, VDDUTMII GNDUTMI
VDDPLLUTMI, VDDPLLA, VDDOSC, GNDOSC
VDDANA GNDANA
15
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
6. Processor and Architecture
6.1 ARM926EJ-S Processor
z RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
z Two Instruction Sets
z ARM High-performance 32-bit Instruction Set
z Thumb High Code Density 16-bit Instruction Set
z DSP Instruction Extensions
z 5-Stage Pipeline Architecture:
z Instruction Fetch (F)
z Instruction Decode (D)
z Execute (E)
z Data Memory (M)
z Register Write (W)
z 32-KByte Data Cache, 32-KByte Instruction Cache
z Virtually-addressed 4-way Associative Cache
z Eight words per line
z Write-through and Write-back Operation
z Pseudo-random or Round-robin Replacement
z Write Buffer
z Main Write Buffer with 16-word Data Buffer and 4-address Buffer
z DCache Write-back Buffer with 8-word Entries and a Single Address Entry
z Software Control Drain
z Standard ARM v4 and v5 Memory Management Unit (MMU)
z Access Permission for Sections
z Access Permission for large pages and small pages can be specified separately for each quarter of the
page
z 16 embedded domains
z Bus Interface Unit (BIU)
z Arbitrates and Schedules AHB Requests
z Separate Masters for both instruction and data access providing complete Matrix system flexibility
z Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
z On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
z TCM Interface
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

AT91SAM9G45B-CU-999

Mfr. #:
Buy AT91SAM9G45B-CU-999
Manufacturer:
Description:
IC MCU 32BIT 64KB ROM 324TFBGA SAM9G
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet