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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
6.2 Bus Matrix
z 12-layer Matrix, handling requests from 11 masters
z Programmable Arbitration strategy
z Fixed-priority Arbitration
z Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
z Burst Management
z Breaking with Slot Cycle Limit Support
z Undefined Burst Length Support
z One Address Decoder provided per Master
z Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for
internal flash boot, one after remap
z Boot Mode Select
z Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
z Selection is made by General purpose NVM bit sampled at reset
z Remap Command
z Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
z Allows Handling of Dynamic Exception Vectors
6.2.1 Matrix Masters
The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with others,
depending on whether the slave it accesses is available.
Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.
Table 6-1. List of Bus Matrix Masters
Master 0 ARM926
™
Instruction
Master 1 ARM926 Data
Master 2 Peripheral DMA Controller (PDC)
Master 3 USB HOST OHCI
Master 4 DMA
Master 5 DMA
Master 6 ISI Controller DMA
Master 7 LCD DMA
Master 8 Ethernet MAC DMA
Master 9 USB Device High Speed DMA
Master 10 USB Host High Speed EHCI DMA
