AT91SAM9G45B-CU-999 Datasheet AT91SAM9G45C-CU, AT91SAM9G45C-CU-999, AT91SAM9G45B-CU | P25-P27

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926

data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and

by the AHB Masters through the AHB bus.

z Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is

performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.

After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926

Instruction and the ARM926 Data Masters.

Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is software programmable

according to Table 7-1.

7.2.3 Internal ROM

The SAM9G45 embeds an Internal ROM, which contains the Boot ROM and SAM-BA program.

At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset

and before the Remap Command.

7.2.4 Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possibilities the memory layout can be changed with

two parameters.

REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once

the system has boot.

BMS allows the user to lay out to 0x0, when convenient, the ROM or an external memory. This is done by a hardware

way at reset.

Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these

parameters.

The SAM9G45 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal

memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.

If BMS is detected at 1, the boot memory is the embedded ROM.

If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.

7.2.4.1 BMS = 1, boot on embedded ROM

The system boots on Boot Program.

z Boot on on-chip RC

z Enable the 32768 Hz oscillator

z Auto baudrate detection

z Downloads and runs an application from external storage media into internal SRAM

z Downloaded code size depends on embedded SRAM size

z Automatic detection of valid application

Table 7-1. ITCM and DTCM Memory Configuration

SRAM A ITCM size (KBytes)

seen at 0x100000 through

AHB

SRAM B DTCM size (KBytes)

seen at 0x200000 through

AHB

SRAM C (KBytes)

seen at 0x300000 through

AHB

0064

0640

32 32 0

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z Bootloader on a non-volatile memory

z SPI DataFlash/Serial Flash connected on NPCS0 of the SPI0

z SDCard

z Nand Flash

z EEPROM connected on TWI0

z SAM-BA Boot in case no valid program is detected in external NVM, supporting

z Serial communication on a DBGU

z USB Device HS Port

7.2.4.2 BMS = 0, boot on external memory

z Boot on on-chip RC

z Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write

controlled by Chip Select, allows boot on 16-bit non-volatile memory.

For optimization purpose, nothing else is done. To speed up the boot sequence user programmed software should

perform a complete configuration:

z Enable the 32768 Hz oscillator if best accuracy needed

z Program the PMC (main oscillator enable or bypass mode)

z Program and Start the PLL

z Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to the new clock

z Switch the main clock to the new value

7.3 External Memories

The SAM9G45 features a Multi-port DDR2 Interface and an External Bus Interface allowing to connect to a wide range of

external memories and to any parallel peripheral.

7.3.1 DDRSDRC0 Multi-port DDRSDR Controller

Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency.

z Supports AHB Transfers:

z Word, Half Word, Byte Access.

z Supports DDR2, LPDDR

z Numerous Configurations Supported

z 2K, 4K, 8K, 16K Row Address Memory Parts

z DDR2 with Four Internal Banks

z DDR2/LPDDR with 16-bit Data Path

z One Chip Select for DDR2/LPDDR Device (256 Mbytes Address Space)

z Programming Facilities

z Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of

Transactions)

z Timing Parameters Specified by Software

z Automatic Refresh Operation, Refresh Rate is Programmable

z Automatic Update of DS, TCR and PASR Parameters

z Energy-saving Capabilities

z Self-refresh, Power-down and Deep Power Modes Supported

z Power-up Initialization by Software

z CAS Latency of 2, 3 Supported

z Reset function supported (DDR2)

z Auto Precharge Command Not Used

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z On Die Termination not supported

z OCD mode not supported

7.3.2 External Bus Interface

z Integrates Three External Memory Controllers:

z Static Memory Controller

z DDR2/SDRAM Controller

z SLC Nand Flash ECC Controller

z Additional logic for NAND Flash

and CompactFlash

z Optional Full 32-bit External Data Bus

z Up to 26-bit Address Bus (up to 64MBytes linear per chip select)

z Up to 6 chip selects, Configurable Assignment:

z Static Memory Controller on NCS0

z DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1

z Static Memory Controller on NCS2

z Static Memory Controller on NCS3, Optional NAND Flash support

z Static Memory Controller on NCS4 - NCS5, Optional CompactFlash

support

7.3.2.1 Static Memory Controller

z 8-, 16- or 32-bit Data Bus

z Multiple Access Modes supported

z Byte Write or Byte Select Lines

z Asynchronous read in Page Mode supported (4- up to 32-byte page size)

z Multiple device adaptability

z Control signals programmable setup, pulse and hold time for each Memory Bank

z Multiple Wait State Management

z Programmable Wait State Generation

z External Wait Request

z Programmable Data Float Time

z Slow Clock mode supported

7.3.2.2 DDR2/SDR Controller

z Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR

z Numerous Configurations Supported

z 2K, 4K, 8K, 16K Row Address Memory Parts

z SDRAM with Four Internal Banks

z SDR-SDRAM with 16- or 32- bit Data Path

z DDR2/LPDDR with 16- bit Data Path

z One Chip Select for SDRAM Device (256 Mbyte Address Space)

z Programming Facilities

z Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of

Transactions)

z Timing Parameters Specified by Software

z Automatic Refresh Operation, Refresh Rate is Programmable

z Automatic Update of DS, TCR and PASR Parameters (LPSDR)

z Energy-saving Capabilities

z Self-refresh, Power-down and Deep Power Modes Supported

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AT91SAM9G45B-CU-999

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IC MCU 32BIT 64KB ROM 324TFBGA SAM9G

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AT91SAM9G45B-CU-999

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