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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
8.3 Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU
rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset
signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a
manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
8.4 Shut Down Controller
The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the
pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power
supply.
8.5 Clock Generator
The Clock Generator is made up of:
z One Low Power 32768 Hz Slow Clock Oscillator with bypass mode
z One Low-Power RC oscillator
z One 12 MHz Main Oscillator, which can be bypassed
z One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the
peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the
only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro.
Figure 8-2. Clock Generator Block Diagram
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLLA and
Divider
PLLA Clock
PLLACK
12M Main
Oscillator
UPLL
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
RCEN
UPLLCK
OSCSEL
OSC32EN
OSC32B P
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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
8.6 Slow Clock Selection
The SAM9G45 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The
32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32.
The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respectively RCEN bit and
OSC32EN bit in the system controller user interface. OSCSEL command selects the slow clock source.
RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the slow clock control register (SCKCR) located at
address 0xFFFFFD50 in the backup part of the system controller and so are preserved while VDDBU is present.
Figure 8-3. Slow Clock
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0 allowing the
system to start on the internal RC oscillator.
The programmer controls by software the slow clock switching and so must take precautions during the switching phase.
8.6.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal
To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute the following sequence:
z Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator) through the Power
Management Controller.
z Enable the 32768 Hz oscillator by setting the bit OSCEN to 1.
z Wait 32768 Hz startup time for clock stabilization (software loop).
z Switch from internal RC to 32768 Hz by setting the bit OSCSEL to 1.
z Wait 5 slow clock cycles for internal resynchronization.
z Disable the RC oscillator by setting the bit RCEN to 0.
8.6.2 Bypass the 32768 Hz Oscillator
The following step must be added to bypass the 32768 Hz Oscillator.
z An external clock must be connected on XIN32.
z Enable the bypass path OSC32BYP bit set to 1.
z Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
8.6.3 Switch from 32768 Hz Crystal to the Internal RC Oscillator
The same procedure must be followed to switch from 32768 Hz crystal to the internal RC oscillator.
z Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator).
z Enable the internal RC oscillator by setting the bit RCEN to 1.
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
OSC32EN
RCEN
OSCSEL
OSC32B P
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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
z Wait internal RC Startup Time for clock stabilization (software loop).
z Switch from 32768 Hz oscillator to internal RC oscilllator by setting the bit OSCSEL to 0.
z Wait 5 slow clock cycles for internal resynchronization.
z Disable the 32768Hz oscillator by setting the bit OSC32EN to 0.
8.7 Power Management Controller
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
z UPLLCK: From UTMI PLL
z PLLACK From PLLA
z SLCK: slow clock from OSC32K or internal RC OSC
z MAINCK: from 12 MHz external oscillator
PMC output clocks
z Processor Clock PCK
z Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be 1,2,3 or 4
z DDR system clock equal to 2xMCK
Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
z USB Host EHCI High speed clock (UPLLCK)
z USB OHCI clocks (UHP48M and UHP12M)
z Independent peripheral clocks, typically at the frequency of MCK
z Two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
z Normal Mode, processor and peripherals running at a programmable frequency
z Idle Mode, processor stopped waiting for an interrupt
z Slow Clock Mode, processor and peripherals running at low frequency
z Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for
an interrupt
z Backup Mode, Main Power Supplies off, VDDBU powered by a battery

AT91SAM9G45B-CU-999

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Description:
IC MCU 32BIT 64KB ROM 324TFBGA SAM9G
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