AT91SAM9G45B-CU-999 Datasheet AT91SAM9G45C-CU, AT91SAM9G45C-CU-999, AT91SAM9G45B-CU | P46-P48

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z Common clock generator, providing Thirteen Different Clocks

z A Modulo n counter providing eleven clocks

z Two independent Linear Dividers working on modulo n counter outputs

z Independent channel programming

z Independent Enable Disable Commands

z Independent Clock Selection

z Independent Period and Duty Cycle, with Double Buffering

z Programmable selection of the output waveform polarity

z Programmable center or left aligned output waveform

10.8 High Speed Multimedia Card Interface (MCI)

z Compatibility with MultiMedia Card Specification Version 4.3

z Compatibility with SD Memory Card Specification Version 2.0

z Compatibility with SDIO Specification Version V2.0.

z Compatibility with Memory Stick PRO

z Compatibility with CE ATA

10.9 USB High Speed Host Port (UHPHS)

z Compliant with Enhanced HCI Rev 1.0 Specification

z Compliant with USB V2.0 High-speed and Full-speed Specification

z Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices

z Compliant with Open HCI Rev 1.0 Specification

z Compliant with USB V2.0 Full-speed and Low-speed Specification

z Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices

z Root Hub Integrated with 2 Downstream USB Ports

z Shared Embedded USB Transceivers

10.10 USB High Speed Device Port (UDPHS)

z USB V2.0 high-speed compliant, 480 MBits per second

z Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS.

z Embedded 4-KByte dual-port RAM for endpoints

z Embedded 6 channels DMA controller

z Suspend/Resume logic

z Up to 2 or 3 banks for isochronous and bulk endpoints

z Seven endpoints:

z Endpoint 0: 64 bytes, 1 bank mode

z Endpoint 1 & 2: 1024 bytes, 2 banks mode, High Bandwidth, DMA

z Endpoint 3 & 4: 1024 bytes, 3 banks mode, DMA

z Endpoint 5 & 6: 1024 bytes, 3 banks mode, High Bandwidth, DMA

10.11 LCD Controller (LCDC)

z Single and Dual scan color and monochrome passive STN LCD panels supported

z Single scan active TFT LCD panels supported.

z 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported

z Up to 24-bit single scan TFT interfaces supported

z Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN

z 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN

z 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT

z Single clock domain architecture

z Resolution supported up to 2048 x 2048

10.12 Touch Screen Analog-to-Digital Converter (TSADC)

z 8-channel ADC

z Support 4-wire resistive Touch Screen

z 10-bit 384 Ksamples/sec. Successive Approximation Register ADC

z -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity

z Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

z External voltage reference for better accuracy on low voltage inputs

z Individual enable and disable of each channel

z Multiple trigger sources

z Hardware or software trigger

z External trigger pin

z Sleep Mode and conversion sequencer

z Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels

10.13 Ethernet 10/100 MAC (EMAC)

z Compatibility with IEEE Standard 802.3

z 10 and 100 MBits per second data throughput capability

z Full- and half-duplex operations

z MII or RMII interface to the physical layer

z Register Interface to address, data, status and control registers

z DMA Interface, operating as a master on the Memory Controller

z Interrupt generation to signal receive and transmit completion

z 128-byte transmit and 128-byte receive FIFOs

z Automatic pad and CRC generation on transmitted frames

z Address checking logic to recognize four 48-bit addresses

z Supports promiscuous mode where all valid frames are copied to memory

z Supports physical layer management through MDIO interface

z Supports Wake On Lan. The receiver supports Wake on LAN by detecting the following events on incoming

receive frames:

z Magic packet

z ARP request to the device IP address

z Specific address 1 filter match

z Multicast hash filter match

10.14 Image Sensor Interface (ISI)

z ITU-R BT. 601/656 8-bit mode external interface support

z Support for ITU-R BT.656-4 SAV and EAV synchronization

z Vertical and horizontal resolutions up to 2048 x 2048

z Preview Path up to 640*480

z Support for packed data formatting for YCbCr 4:2:2 formats

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

z Preview scaler to generate smaller size image

10.15 8-channel DMA (DMA)

z Acting as two Matrix Masters

z Embeds 8 unidirectional channels with programmable priority

z Address Generation

z Source/Destination address programming

z Address increment, decrement or no change

z DMA chaining support for multiple non-contiguous data blocks through use of linked lists

z Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of

data into non-contiguous fields in system memory

z Gather support for extracting fields from a system memory area into a contiguous transfer

z User enabled auto-reloading of source, destination and control registers from initially programmed values at

the end of a block transfer

z Auto-loading of source, destination and control registers from system memory at end of block transfer in

block chaining mode

z Unaligned system address to data transfer width supported in hardware

z Channel Buffering

z 16-word FIFO

z Automatic packing/unpacking of data to fit FIFO width

z Channel Control

z Programmable multiple transaction size for each channel

z Support for cleanly disabling a channel without data loss

z Suspend DMA operation

z Programmable DMA lock transfer support

z Transfer Initiation

z Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a

DMA transfer in place of a hardware handshaking interface

z Interrupt

z Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple

transaction completion or Error condition

10.16 True Random Number Generator (TRNG)

z Passed NIST Special Publication 800-22 Tests Suite

z Passed Diehard Random Tests Suite

z Provides a 32-bit Random Number Every 84 Clock Cycles

z For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AT91SAM9G45B-CU-999

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IC MCU 32BIT 64KB ROM 324TFBGA SAM9G

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AT91SAM9G45B-CU-999

AT91SAM9G45B-CU-999

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