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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
9.4.5 PIO Controller E Multiplexing
Table 9-6. Multiplexing on PIO Controller E (PIOE)
I/O Line Peripheral A Peripheral B
Reset
State
Power
Supply Function Comments
PE0 LCDPWR PCK0 I/O VDDIOP1
PE1 LCDMOD I/O VDDIOP1
PE2 LCDCC I/O VDDIOP1
PE3 LCDVSYNC I/O VDDIOP1
PE4 LCDHSYNC I/O VDDIOP1
PE5 LCDDOTCK I/O VDDIOP1
PE6 LCDDEN I/O VDDIOP1
PE7 LCDD0 LCDD2 I/O VDDIOP1
PE8 LCDD1 LCDD3 I/O VDDIOP1
PE9 LCDD2 LCDD4 I/O VDDIOP1
PE10 LCDD3 LCDD5 I/O VDDIOP1
PE11 LCDD4 LCDD6 I/O VDDIOP1
PE12 LCDD5 LCDD7 I/O VDDIOP1
PE13 LCDD6 LCDD10 I/O VDDIOP1
PE14 LCDD7 LCDD11 I/O VDDIOP1
PE15 LCDD8 LCDD12 I/O VDDIOP1
PE16 LCDD9 LCDD13 I/O VDDIOP1
PE17 LCDD10 LCDD14 I/O VDDIOP1
PE18 LCDD11 LCDD15 I/O VDDIOP1
PE19 LCDD12 LCDD18 I/O VDDIOP1
PE20 LCDD13 LCDD19 I/O VDDIOP1
PE21 LCDD14 LCDD20 I/O VDDIOP1
PE22 LCDD15 LCDD21 I/O VDDIOP1
PE23 LCDD16 LCDD22 I/O VDDIOP1
PE24 LCDD17 LCDD23 I/O VDDIOP1
PE25 LCDD18 I/O VDDIOP1
PE26 LCDD19 I/O VDDIOP1
PE27 LCDD20 I/O VDDIOP1
PE28 LCDD21 I/O VDDIOP1
PE29 LCDD22 I/O VDDIOP1
PE30 LCDD23 I/O VDDIOP1
PE31 PWM2 PCK1 I/O VDDIOP1
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SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
10. Embedded Peripherals
10.1 Serial Peripheral Interface (SPI)
z Supports communication with serial external devices
z Four chip selects with external decoder support allow communication with up to 15 peripherals
z Serial memories, such as DataFlash and 3-wire EEPROMs
z Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
z External co-processors
z Master or slave serial peripheral bus interface
z 8- to 16-bit programmable data length per chip select
z Programmable phase and polarity per chip select
z Programmable transfer delays between consecutive transfers and between clock and data per chip select
z Programmable delay between consecutive transfers
z Selectable mode fault detection
z Very fast transfers supported
z Transfers with baud rates up to MCK
z The chip select line may be left active to speed up transfers on the same device
10.2 Two Wire Interface (TWI)
z Compatibility with standard two-wire serial memory
z One, two or three bytes for slave address
z Sequential read/write operations
z Supports either master or slave modes
z Compatible with Standard Two-wire Serial Memories
z Master, Multi-master and Slave Mode Operation
z Bit Rate: Up to 400 Kbits
z General Call Supported in Slave mode
z Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode
Only
z One Channel for the Receiver, One Channel for the Transmitter
z Next Buffer Support
10.3 Universal Synchronous Asynchronous Receiver Transmitter (USART)
z Programmable Baud Rate Generator
z 5- to 9-bit full-duplex synchronous or asynchronous serial communications
z 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
z Parity generation and error detection
z Framing error detection, overrun error detection
z MSB- or LSB-first
z Optional break generation and detection
z By 8 or by-16 over-sampling receiver frequency
z Hardware handshaking RTS-CTS
z Receiver time-out and transmitter timeguard
z Optional Multi-drop Mode with address generation and detection
z Optional Manchester Encoding
45
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
z RS485 with driver control signal
z ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
z NACK handling, error counter with repetition and iteration limit
z IrDA modulation and demodulation
z Communication at up to 115.2 Kbps
z Test Modes
z Remote Loopback, Local Loopback, Automatic Echo
10.4 Serial Synchronous Controller (SSC)
z Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master
or Slave Modes, I
2
S, TDM Buses, Magnetic Card Reader,...)
z Contains an independent receiver and transmitter and a common clock divider
z Offers a configurable frame sync and data length
z Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
z Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.5 AC97 Controller
z Compatible with AC97 Component Specification V2.2
z Capable to Interface with a Single Analog Front end
z Three independent RX Channels and three independent TX Channels
z One RX and one TX channel dedicated to the AC97 Analog Front end control
z One RX and one TX channel for data transfers, associated with a PDC
z One RX and one TX channel for data transfers with no PDC
z Time Slot Assigner allowing to assign up to 12 time slots to a channel
z Channels support mono or stereo up to 20 bit sample length
z Variable sampling rate AC97 Codec Interface (48KHz and below)
10.6 Timer Counter (TC)
z Three 16-bit Timer Counter Channels
z Wide range of functions including:
z Frequency Measurement
z Event Counting
z Interval Measurement
z Pulse Generation
z Delay Timing
z Pulse Width Modulation
z Up/down Capabilities
z Each channel is user-configurable and contains:
z Three external clock inputs
z Five internal clock inputs
z Two multi-purpose input/output signals
z Two global registers that act on all three TC Channels
10.7 Pulse Width Modulation Controller (PWM)
z Four channels, one 16-bit counter per channel

AT91SAM9G45B-CU-999

Mfr. #:
Manufacturer:
Description:
IC MCU 32BIT 64KB ROM 324TFBGA SAM9G
Lifecycle:
New from this manufacturer.
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