20
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
6.3 Peripheral DMA Controller (PDC)
z Acting as one AHB Bus Matrix Master
z Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
z Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
6.4 USB
The SAM9G45 features USB communication ports as follows:
z 2 Ports USB Host full speed OHCI and High speed EHCI
z 1 Device High speed
USB Host Port A is directly connected to the first UTMI transceiver.
The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port. The selection
between Host Port B and USB device high speed is controlled by a the bit UDPHS enable bit located in the
UDPHS_CTRL control register.
Table 6-6. Peripheral DMA Controller
Instance name Channel T/R
DBGU Transmit
USART3 Transmit
USART2 Transmit
USART1 Transmit
USART0 Transmit
AC97C Transmit
SPI1 Transmit
SPI0 Transmit
SSC1 Transmit
SSC0 Transmit
TSADCC Receive
DBGU Receive
USART3 Receive
USART2 Receive
USART1 Receive
USART0 Receive
AC97C Receive
SPI1 Receive
SPI0 Receive
SSC1 Receive
SSC0 Receive
